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On-Chip Decoupling Capacitors for VLSI Gate Array and Master Image Products

IP.com Disclosure Number: IPCOM000034270D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Fitzgerald, FC: AUTHOR [+3]

Abstract

A method is shown for bringing electrical charge closer to the active circuits on a very large-scale integrated (VLSI) master slice or standard cell chip product which provides for a reduction in noise by capacitive decoupling at the chip rather than at the module or card level. A typical gate array chip layout is shown in Fig. 1 which includes circuit bays 10, wiring bays 11 and I/O cells 12 on the perimeter of the chip. VLSI logic circuits fabricated with only two or three levels of metal are often wire-limited. Therefore, the multi-level wiring bays used to interconnect devices in the logic bays have unused area which the technology cannot utilize for all possible circuits on a chip.

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On-Chip Decoupling Capacitors for VLSI Gate Array and Master Image Products

A method is shown for bringing electrical charge closer to the active circuits on a very large-scale integrated (VLSI) master slice or standard cell chip product which provides for a reduction in noise by capacitive decoupling at the chip rather than at the module or card level. A typical gate array chip layout is shown in Fig. 1 which includes circuit bays 10, wiring bays 11 and I/O cells 12 on the perimeter of the chip. VLSI logic circuits fabricated with only two or three levels of metal are often wire-limited. Therefore, the multi-level wiring bays used to interconnect devices in the logic bays have unused area which the technology cannot utilize for all possible circuits on a chip. Historically, the unused areas in the wiring bays are not isolated by the wired logic, therefore, the free areas may be utilized to incorporate on-chip decoupling capacitors. The optimum capacitor possible for a particular chip is a function of the devices available within the device bays that may be available to form on-chip decoupling capacitors. The resistive and capacitive characteristics of the available devices are also a consideration. A capacitor structure that can be implemented in the wiring bays is shown in Fig. 2. The figure shows the top and cross-section A-A view of a N-channel field-effect transistor (NFET) structure with a first level metal (M1) 13, insulator 14, a polysilicon layer 15, a t...