Browse Prior Art Database

Bipolar/Cmos SRAM Cell

IP.com Disclosure Number: IPCOM000034272D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Dittrich, MS: AUTHOR [+4]

Abstract

Low-power static random-access memory (SRAM) designs, particularly those using battery back-up, necessitate the use of CMOS in the array. The chip performance can be increased by using bipolar structures in the access path. The unique CMOS process disclosed here utilizes only eleven masking steps to a first level metal and is compatible with bipolar designs. (Image Omitted) Referring to Fig. 1, the common NMOS source 10 and 11 is connected to ground while the common PMOS source 12 and 13 is connected to VH . In conventional designs, the connections necessitate additional wiring paths utilizing one of the metal levels. The disclosed process provides buried layers for these connections, as shown in Figs. 3 and 4, thus reducing the cell size. The main process features are illustrated in Figs. 2, 3 and 4.

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Bipolar/Cmos SRAM Cell

Low-power static random-access memory (SRAM) designs, particularly those using battery back-up, necessitate the use of CMOS in the array. The chip performance can be increased by using bipolar structures in the access path. The unique CMOS process disclosed here utilizes only eleven masking steps to a first level metal and is compatible with bipolar designs.

(Image Omitted)

Referring to Fig. 1, the common NMOS source 10 and 11 is connected to ground while the common PMOS source 12 and 13 is connected to VH . In conventional designs, the connections necessitate additional wiring paths utilizing one of the metal levels. The disclosed process provides buried layers for these connections, as shown in Figs. 3 and 4, thus reducing the cell size. The main process features are illustrated in Figs. 2, 3 and 4. A first mask defines the buried N+ layers 10 and 11, and 12 and 13 in a semiconductor substrate 9. The buried layers, heavily doped with arsenic or antimony, are used to suppress latch-up in CMOS structures, to reduce the collector resistance in bipolar npn transistors and also as an underpass for ground and VH connections. The step 14 created at the perimeter of the buried layer shown in Fig. 2 is used for alignment of subsequent masks. The step propagates through the n-type epitaxy 15 which is grown next, as shown in Fig. 3. The thickness and surface concentration of the epitaxial layer 15 are typically 1 to 2 mm and approximately 4x1016 cm-3, respectively. A second mask is used to define trenches 16 in the epitaxial layer 15 (Fig. 3). The alignment step is not shown. After being filled with, e.g., heavily doped n-type polysilicon, and planarized, the trenches provide connections to the buried layer...