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Flex Drive Spindle Motor Acceleration Test Circuit

IP.com Disclosure Number: IPCOM000034278D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Ho, JPL: AUTHOR [+2]

Abstract

The test circuit, as shown in Fig. 1, is used to provide an output voltage Vo that is directly proportional to acceleration (speed variation) of a flexible disk drive spindle motor. Read Data pulses from the disk drive originate from a precision written if pattern on a diskette. These pulses are equally spaced in time when there is no motor speed variation. For speed variations, these pulses are not equally spaced in time. It is this unequal spacing that represents spindle motor speed variation. During operation of the test circuit, Read Data pulses are applied at 1. Circuit 20 is a divide by 4 circuit used to remove read channel asymmetry. Signals on lines 2 and 3 provide self-timing for the test circuit. The overall function of the test circuit can most easily be understood by observing the timing signals at 1 and 8.

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Flex Drive Spindle Motor Acceleration Test Circuit

The test circuit, as shown in Fig. 1, is used to provide an output voltage Vo that is directly proportional to acceleration (speed variation) of a flexible disk drive spindle motor. Read Data pulses from the disk drive originate from a precision written if pattern on a diskette. These pulses are equally spaced in time when there is no motor speed variation. For speed variations, these pulses are not equally spaced in time. It is this unequal spacing that represents spindle motor speed variation. During operation of the test circuit, Read Data pulses are applied at 1. Circuit 20 is a divide by 4 circuit used to remove read channel asymmetry. Signals on lines 2 and 3 provide self-timing for the test circuit. The overall function of the test circuit can most easily be understood by observing the timing signals at 1 and 8. Signal input timing at 1 is broken up, as illustrated in Fig. 2, into time segments a, b, c, d, e, f, g, etc. Signal output timing at 8 is proportional to b-a, c-b, d-c, e-d, f-e, g-f, etc., which is proportional to speed variation.

(Image Omitted)

Circuits 21 and 22 are sample and hold integrators used to provide outputs proportional to the time measured segments. Circuits 23 and 24 are sample and hold amplifiers used to sample the time measured outputs at 4 and 5, respectively.

The output at 8 is for the following input time segments at 1: b = a

* c < b

* d > c

e = d

* f < e

g = f where * represe...