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Programmable Equals Comparator With Multiple Trigger Capability

IP.com Disclosure Number: IPCOM000034282D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Knight, SA: AUTHOR

Abstract

The comparator basically receives two simultaneous inputs and produces outputs that indicate if the inputs are greater than, less than, or equal to each other. In many scenarios, the equals condition is all that is of interest. This comparator allows multiple predefined input data patterns to be uniquely identified for an equals compare condition. The comparator is built by using static random-access memory (RAM) 10 as a hardware look-up table. This is done by using the address lines of the RAM 20, as the pattern to be interrogated for an equals condition. If a pattern is pre-programmed for an equals match, a data bit 30 from the RAM should become active whenever that pattern is present on its address lines.

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Programmable Equals Comparator With Multiple Trigger Capability

The comparator basically receives two simultaneous inputs and produces outputs that indicate if the inputs are greater than, less than, or equal to each other. In many scenarios, the equals condition is all that is of interest. This comparator allows multiple predefined input data patterns to be uniquely identified for an equals compare condition. The comparator is built by using static random-access memory (RAM) 10 as a hardware look-up table. This is done by using the address lines of the RAM 20, as the pattern to be interrogated for an equals condition. If a pattern is pre-programmed for an equals match, a data bit 30 from the RAM should become active whenever that pattern is present on its address lines. As this data bit becomes active and the hardware is set in the correct mode 35, an output signal 40, may be used in conjunction with the input pattern 45, to uniquely identify the match condition. Therefore, the width of a compare is equal to the number of address lines the RAM supports. In order to program RAM 20 so that it may be used in this fashion, some support logic is required to cycle through RAM 20 to initialize it. This is accomplished by a set of registers 50, 60, 70 that can be used to control the address lines 20, the data lines 80, and control lines 90, 100, 110 of the RAM in a controlled way. The figure shows an example of how this technique is used for an 8-bit-wide comparator. If the static RAM 10 being used has multiple output data bits, the other data bits 120 may be programmed as a vector for the compare. That is to say, these bits may be used to further qualify or be the source to trigger other hardware activity due to a compare. The number of unique vectors that can be produced is a function of the RAM...