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Method and Arrangement for Testing Switch-Network Components

IP.com Disclosure Number: IPCOM000034285D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Tsui, FF: AUTHOR

Abstract

In a parallel-processor system operating with packet-switching of messages, an essential part is the switch-network interconnecting the various processing and memory elements. This article describes a method for testing switch-network components at high speeds, and the design of test-messages to facilitate such testing. (Image Omitted) Principle of Test Method: Test-Data Loopback: To achieve near-at-speed (multiple-consecutive-cycle) testing, a basic concept of test-data loopback can be used, whereby (see in Fig. 1) the test-object's data-outputs (DOs) are fed back to its data-inputs (DIs). (Image Omitted) The storage-elements (latches) within the test-object capture the test-results at the end of each cycle; this, together with the loopback, allows the results to be used as new test-inputs for the next cycle.

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Method and Arrangement for Testing Switch-Network Components

In a parallel-processor system operating with packet-switching of messages, an essential part is the switch-network interconnecting the various processing and memory elements. This article describes a method for testing switch-network components at high speeds, and the design of test-messages to facilitate such testing.

(Image Omitted)

Principle of Test Method: Test-Data Loopback:

To achieve near-at-speed (multiple-consecutive-cycle) testing, a basic concept of test-data loopback can be used, whereby (see in Fig. 1) the test-object's data-outputs (DOs) are fed back to its data-inputs (DIs).

(Image Omitted)

The storage-elements (latches) within the test-object capture the test-results at the end of each cycle; this, together with the loopback, allows the results to be used as new test-inputs for the next cycle. Swapping of Connections in Loopback: The test-object's data-outputs are fed back to its data-inputs via additional, external connections. In the loopback, connections can be swapped; this can be introduced at two levels:

(Image Omitted)

Port-level: Lines pertaining to a data-out port with

index J are fed

back, as a group without any change in their

order, to the lines of a data-in port with a

different index: DO(J) ---T DI(not-J), where

J = 0, 1, 2, or 3 for a 4-way switch, and

"---T" denotes an external loopback

connection.

(Image Omitted)

Line-Level:Lines (with indices i = 0,

1, ... to nl, not including

the parity-bit and data-valid lines)

pertaining to a data-out with index J are fed

back, in a changed order, to the lines of the

data-in port with the same index J: DO(J)i

---T DI(J)not-i . As illustrated in Fig. 2, there can be four possible ways for implementing the loopback connections:

(Image Omitted)

1

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(a) No-swap:

DO(J)i ---T DI(J)i (b) Port-swap-only: DO(J)i ---T DI(not-J)i

(c) Line-swap-only: DO(J)i ---T DI(J)not-i

(d) Port-and-line-swap: DO(J)i ---T DI(not-J)not-i For loopback-testing a switch-network component, a line-swap in any manner can offer the advantage that if the test is run for a number (Nc) of consecutive cycles, and if the component be looked upon as a "state-machine", the loopback is virtually equivalent to cascading Nc such state-machines in series, so that errors occurring in a data-line will have a greatly reduced probability of becoming masked ("aliased") by other errors in that same line. [The probability is zero, if the number of cycles (Nc) through which the test is run is chosen not larger than the number of data-lines (nl) pertaining to a port. In practice, this may (except when intermittent errors need to be traced) even be a preferred short way of testing-out small switch-network components.] A line-swap in a systematic manner, on the other hand, can (besides being less confusing and more easily manageable) allow additional useful features to be incorporated. Among these is a capability, to be described below, for au...