Browse Prior Art Database

DIAGNOSIS of ARRAY Failures in a Self-Test Environment

IP.com Disclosure Number: IPCOM000034287D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 16K

Publishing Venue

IBM

Related People

Gupta, VP: AUTHOR [+3]

Abstract

An array diagnostic methodology is described for a self-test environment. Array defects are diagnosed using both logic test and array test. Logic test diagnosis is more efficient than array test diagnosis. By applying logic test before array test, most of the array defects are diagnosed using logic test. For array test diagnosis: A trace-back analysis identifies the minimum amount of logic that needs to be simulated. The significant events simulator only simulates logic that changes from one pattern to next pattern. No simulation is done for data-in lines. These considerations minimize simulation activity and thus improve performance. PROBLEM STATEMENT The device under consideration is a multi-chip module. The device uses the STUMPS structure for implementing self-test.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 45% of the total text.

Page 1 of 3

DIAGNOSIS of ARRAY Failures in a Self-Test Environment

An array diagnostic methodology is described for a self-test environment. Array defects are diagnosed using both logic test and array test. Logic test diagnosis is more efficient than array test diagnosis. By applying logic test before array test, most of the array defects are diagnosed using logic test. For array test diagnosis: A trace-back analysis identifies the minimum amount of

logic that needs to be simulated.

The significant events simulator only simulates logic

that changes from one pattern to next pattern.

No simulation is done for data-in lines. These considerations minimize simulation activity and thus improve performance. PROBLEM STATEMENT The device under consideration is a multi-chip module. The device uses the STUMPS structure for implementing self-test. The pseudo- random pattern generator (PRPG) generates a large number of random patterns that are loaded in the shift register latches (SRLs).

The response data captured by the SRLs is compressed in the multiple-input signature register (MISR). At the end of the test, the MISR signature is compared with precalculated good signature to make a pass/fail determination. There are two types of tests: logic test and array test. Logic test is intended to detect faults associated with logic. Array test is intended to detect faults associated with arrays. For failing devices, the tester collects additional data for diagnosis. First, the failure is isolated to a failing STUMPS channel. Then the failure is isolated to a group of 256 test patterns. The tester collects response data for all of the SRLs in the failing STUMPS channel for the 256 patterns. The data collection procedure is the same for both logic test and array test.

During the array test, random data is written into and read from all memory cells a predetermined number of times. Built-in address steppers are used for controlling the array addressing. The address steppers cycle through all 2**n addresses, where n is the number of address lines. Logic test is applied before array test. Array test is applied only if logic test passes. Logic test diagnosis is done using the parallel pattern single fault propagation (PPSFP) simulator. The PPSFP simulator simulates 256 patterns in parallel.

The logic test diagnostic method is described in detail below. Array test diagnosis is done using the significant events good machine simulator. A non-simulation, a full functional simulation or a parallel simulation approach is difficult to use for array test diagnosis. The array test diagnostic method is also described in detail below. Some of the unique features of our approach for array diagnosis are: Array defects are diagnosed using both logic test and

array test. Logic test diagnosis is more efficient

than array test diagnosis. By applying logic test

before array test, most of the array defects are

diagnosed using logic test.

Logic test diagnosis

1

Page 2 of 3

The fault lis...