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Random Pattern Testing of LSSD Logic Devices by Multiple Sets of Weights

IP.com Disclosure Number: IPCOM000034302D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Eichelberger, EB: AUTHOR [+3]

Abstract

VLSI (very large-scale integrated) circuit chips are very difficult to give 100% test coverage to without incurring enormous test generation costs. By use of the algorithm described in this article, together with the application of [1, 2], weighted random pattern (WRP) testing is shown to have the capability of full (100%) test fault coverage in detecting faults in LSSD (level sensitive scan design) logic while achieving a significant reduction in the number of random patterns otherwise required to provide adequate test coverage. The use of weighted random stimuli to test LSSD logic devices [1] is a very powerful way of reducing the number of random patterns necessary to achieve an acceptable test.

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Random Pattern Testing of LSSD Logic Devices by Multiple Sets of Weights

VLSI (very large-scale integrated) circuit chips are very difficult to give 100% test coverage to without incurring enormous test generation costs. By use of the algorithm described in this article, together with the application of [1, 2], weighted random pattern (WRP) testing is shown to have the capability of full (100%) test fault coverage in detecting faults in LSSD (level sensitive scan design) logic while achieving a significant reduction in the number of random patterns otherwise required to provide adequate test coverage. The use of weighted random stimuli to test LSSD logic devices [1] is a very powerful way of reducing the number of random patterns necessary to achieve an acceptable test. However, when attempting to find a single set of weights that tries to satisfy all of the random resistant faults in the circuit, there often occurs a competition of conflicting weights on a single block. If the opposing weights are of equal magnitude, this results in a normal (unweighted) random pattern testability. This competition of weights can occur in structures that contain simple fan-out or reconvergent fan-out with the result that the weighting effects are averaged out with no improvement in the random pattern testability. Thus, while a single set of weighted random patterns can significantly improve the ability of random patterns to achieve adequate test coverage with a reasonable number of patterns, there still exist devices for which weighted random patterns cannot provide a test. The solution to this problem is found by allowing the use of additional sets of weights.

In addition to the global set of weights [1] which attempt to make the entire device testable, additional sets of weights will be created that focus on faults left untested by the weighted random patterns defined by the preceding sets of weights. A very efficient fault simulation has been earlier described [2] for use in evaluating the faults detected by a given set of weights. The disclosed methodology, by use of multiple sets of weights and the previously cited reference, can now be shown to overcome the test deficiency noted and to guarantee that a test is provided for all possible faults on all logic LSSD devices. The algorithm for calculating the multiple sets of weights required to this end consists of the following six steps: 1) Create the set of faults which are desired to be

tested by the weighted random patterns.

2) Calculate the global set of weights by use of [1]

3) Simulate the exact weighted random patterns that

result from the set of weights calculated from

step 2 by the means described in [2] and eliminate

those faults detected. Repeat this procedure for

additional sets of 256 patte...