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Hardware-Generated First Cycle Controls in a Read-Only Storage Controlled Computer

IP.com Disclosure Number: IPCOM000034303D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 1 page(s) / 13K

Publishing Venue

IBM

Related People

Concha, F: AUTHOR [+2]

Abstract

A technique is described whereby the performance of read-only storage (ROS) controlled computers is enhanced by utilizing hardware-generated first cycle control computational logic and by utilizing hardware initiated microcode sequences and first cycle control computational logic. Generally, ROS-controlled computers require a time delay of at least the designated ROS access time so as to generate the first microcode control word. They also require multiple layers of test and branch routines to select the desired microcode for either the instruction processing or system control processing. The concept described herein provides a hardware method of generating the first word, thereby minimizing the access time required for the control word.

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Hardware-Generated First Cycle Controls in a Read-Only Storage Controlled Computer

A technique is described whereby the performance of read-only storage (ROS) controlled computers is enhanced by utilizing hardware-generated first cycle control computational logic and by utilizing hardware initiated microcode sequences and first cycle control computational logic. Generally, ROS-controlled computers require a time delay of at least the designated ROS access time so as to generate the first microcode control word. They also require multiple layers of test and branch routines to select the desired microcode for either the instruction processing or system control processing. The concept described herein provides a hardware method of generating the first word, thereby minimizing the access time required for the control word. Also, all test conditions are grouped into one level of test and branch, thereby minimizing the multiple layer processing time. Typically, microcode controls used in ROS-controlled computers consist of a series of disconnected microcode routines, each of which are selected, initiated and run dependent upon hardware decode instruction or system level function to be performed. If the selected routine is performance oriented, it is preferred to execute the first microcode control word as rapidly as possible so as to maintain high performance. Usually, the ROS used is slow with respect to the speed of the logic hardware and, therefore, requires at least one machine cycle for control word access. This access and address generation time consumes processing time. However, by generating the first control word by means of computational logic, the processing time can be reduced. The first control word is generated by means of computational logic, including the ROS address of the second control word of the routine. While the first control word is being executed, the second contr...