Browse Prior Art Database

NRZI Encoder/Decoder With Jitter-Smoothing Mechanism

IP.com Disclosure Number: IPCOM000034306D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 5 page(s) / 114K

Publishing Venue

IBM

Related People

Chang, LL: AUTHOR [+3]

Abstract

This article describes an algorithm for encoding and decoding of non-return to zero inverted (NRZI) coding with jitter-smoothing mechanism. NRZI data encoding format is one of several popular data encoding formats employed in data communication networks. The jitter is the shifting of the edge of a signal from the nominal position due to the characteristics of the modem being used in the network and the transmission over a length of cable. Smoothing the jitter will improve the quality of the network's data transmission. The encoding rule is rather simple. Data transition only occurs at the bit cell boundary when the original data bit equals 0, and the direction of transition depends upon the present encoded signal level, to 0 if 1 and to 1 if 0.

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NRZI Encoder/Decoder With Jitter-Smoothing Mechanism

This article describes an algorithm for encoding and decoding of non-return to zero inverted (NRZI) coding with jitter-smoothing mechanism. NRZI data encoding format is one of several popular data encoding formats employed in data communication networks. The jitter is the shifting of the edge of a signal from the nominal position due to the characteristics of the modem being used in the network and the transmission over a length of cable. Smoothing the jitter will improve the quality of the network's data transmission. The encoding rule is rather simple. Data transition only occurs at the bit cell boundary when the original data bit equals 0, and the direction of transition depends upon the present encoded signal level, to 0 if 1 and to 1 if 0.

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The implementation of the encoding part of this disclosure is fairly straightforward.

Invert Exclusive-OR the original data and the current encoded data and then clock the outcome with a transmit clock through a D flip-flop so that if the value of the original data is 0, the value of the encoded data will be the inversion of the value of the current encoded data. Otherwise, the next encoded data will remain unchanged. The implementation is done in a programmable array logic (PAL) and an external delay flip-flop. Refer to Fig. 1 for the equations of signal T1 and NRZI and Fig. 2 for the implementation. The decoding principle of this disclosure is to first synchronize the receiving clock with the transmitting clock by adjusting the bit cell 'window' counter so that the transition edge of the incoming encoded data (data transition always happens on bit boundary) will be placed in the center of the window. The synchronizing process can be completed by adjusting the window counter through the preamble bits. Preamble is a series of alternated 0's and 1's being transmitted prior to the real data being transmitted. The decoding is done by detecting the transition edge from the incoming data. If a transition is detected, the next data bit will be decoded as a "0" bit; otherwise, the next data bit will be decoded as a "1" bit. Then, the decoded data will be clocked out by the receiving clock.

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The window counter adjustment process also serves to smooth the jitter. After the synchronizing is accomplished, if a transition is detected off the center of the window then the window will be moved forward or backward in order to place the transition to the center of the window. By doing this, the receiving clock is adjusted. The receiving clock is extracted from the center count of the window counter so that the jitter on the received data will be smoothed out while being clocked out by receiving clock. A twenty-two input, ten output PAL (Advanced Micro

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Devices, Inc. part AM 22V10) was chosen to design a state machine for implementing this algorithm. The PAL is shared by encode and decode mechanism in a personal...