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Post Amplifier and Amplitude Detector Circuit for Magnetic Recording Channels

IP.com Disclosure Number: IPCOM000034307D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 4 page(s) / 93K

Publishing Venue

IBM

Related People

De La Moneda, FH: AUTHOR [+2]

Abstract

A circuit is described for signal amplification and generation of the control signal for automatic gain control (AGC) for magnetic recording channels. The novel concepts underlying these circuits are intimately related to the design in CMOS technology and to the full integration of the circuit. There are no external components such as capacitors or adjustable resistors. Recording channels based on this design approach will be more reliable and much less expensive to manufacture than circuits presently implemented in products which contain many discrete components. (Image Omitted) To make circuits robust, they must be designed such that their behavior does not depend strongly on electrical parameters of the individual components.

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Post Amplifier and Amplitude Detector Circuit for Magnetic Recording Channels

A circuit is described for signal amplification and generation of the control signal for automatic gain control (AGC) for magnetic recording channels. The novel concepts underlying these circuits are intimately related to the design in CMOS technology and to the full integration of the circuit. There are no external components such as capacitors or adjustable resistors. Recording channels based on this design approach will be more reliable and much less expensive to manufacture than circuits presently implemented in products which contain many discrete components.

(Image Omitted)

To make circuits robust, they must be designed such that their behavior does not depend strongly on electrical parameters of the individual components. Measures to obtain the weak dependence on process parameters will be pointed out in the description of the individual circuits. This design approach yields another benefit: Circuits that are not too sensitive to device parameters will also be relatively insensitive to inaccuracies in the simulation models.

This increases the likelihood of obtaining functional circuits in the first design pass, even with less than perfect processing; but more importantly, it ultimately increases the fabrication yield. As a case in point, the first CMOS1 wafers of these circuits may have a number of major parameters significantly outside specified ranges. Nevertheless, circuits that have no catastrophic defects, such as shorts or broken connections, perform closely to the predictions of the simulations, although the simulation models themselves have not been very accurate. Fig. 1 shows the block diagram of the read channel up to the input of the peak detector circuit. The functions of the blocks are the same as in presently used recording channels. The circuit disclosed here is represented by the block at the center of the lower row, including the resistor and capacitor labeled TR and TC, respectively. The element TR is a p-channel MOSFET used as a resistor. The cutoff frequency of the path from node VF to node VE is 16 kHz, so that the potential of the signal at node VE is equal to the long-range average value of the signal at node VF. This circuit represents one way of coupling signals from a single-ended to a differential circuit. The circuit diagram for the circuit represented by the block post amplifier and amplitude detector is shown in Fig.
2. The automatic gain control loop of a read channel is required to adjust the gain of the variable-gain amplifier (VGA) so that the output signal amplitude is practically constant over an amplitude range of the input signal of about 30 : 1. The regulation time constant needs to be sufficiently long to avoid significant distortion of the signal, but still short enough to follow drifts of the input amplitude during read operations. In addition, the AGC should not react to a sudden large drop or disappearan...