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Adder Architecture for Address Generation by a Direct Memory Access Controller

IP.com Disclosure Number: IPCOM000034309D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 5 page(s) / 79K

Publishing Venue

IBM

Related People

Peterson, GA: AUTHOR

Abstract

A conventional Direct Memory Access (DMA) Controller transfers data between a memory location and an I/O port during one cycle. During each DMA cycle, the DMA Controller puts out the address of the memory location along with control information. The control information indicates which direction the data will be transferred and provides timing control. In a conventional DMA Controller design each channel consists of an Address Register, a Block Length Register, and a Control Register. When a given channel gets control, the Address Register and Block Length Register are loaded into an Address Counter and a Block Length Counter. The Address Counter counts up while the Block Length Counter counts down each time a piece of data is transferred. The DMA transfer is complete when the Block Length Counter reaches zero.

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Adder Architecture for Address Generation by a Direct Memory Access Controller

A conventional Direct Memory Access (DMA) Controller transfers data between a memory location and an I/O port during one cycle. During each DMA cycle, the DMA Controller puts out the address of the memory location along with control information. The control information indicates which direction the data will be transferred and provides timing control. In a conventional DMA Controller design each channel consists of an Address Register, a Block Length Register, and a Control Register. When a given channel gets control, the Address Register and Block Length Register are loaded into an Address Counter and a Block Length Counter. The Address Counter counts up while the Block Length Counter counts down each time a piece of data is transferred. The DMA transfer is complete when the Block Length Counter reaches zero. All of the channel registers except the control register change values during a DMA. Because of this, the original values of all of the registers need to be stored if the automatic reload function is desired. This requires a considerable amount of storage. The DMA Controller is required to generate two addresses - a source address and a target address. Using the conventional DMA architecture in this case requires the DMA Controller to store a copy of the Initial Source Address, Initial Target Address, and Block Length Registers for each channel.

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The present adder architecture described below only requires a copy of the Block Length to be stored. This reduces the amount of storage needed for the automatic reload function. A DMA Controller may have 8 channels which transfer 64K byte blocks of data from one memory location to another using a 24-bit address. Using these numbers, a conventional design would need 64 bytes of registers to store the address and block length information needed for the automatic reload function. This adder architecture hereof reduces the requirement for this example to 16 bytes. The logic in a multiple channel DMA controller can be divided into two parts: logic which is unique to individual channels and common logic shared by all channels. Logic unique to individual channels consists of storage locations for addresses, block lengths, and channel-unique control information. Logic common to all channels includes bus control, data processing, error detection, and address generation. This architecture provides a way for the common logic to generate addresses which reduces the requirement for address and block length storage. This is described below using a serial DMA controller for an example, but it may also be used in a parallel DMA controller. A serial DMA Controller generates two addresses during each DMA transfer, while a parallel DMA controller generates only one address during a transfer. This architecture implements a DMA Controller which uses the automatic reload function. The architecture shown here is...