Browse Prior Art Database

Trench Butted Lateral PNP Transistor

IP.com Disclosure Number: IPCOM000034320D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 4 page(s) / 135K

Publishing Venue

IBM

Related People

Hsieh, CM: AUTHOR [+2]

Abstract

This article concerns a process for making a deep trench butted-free lateral PNP transistor (LPNP) having much lower parasitic PFET channel current than a conventional device employing polysilicon-filled deep trench isolation. The disclosed device can be made on a conventional NPN process line without need of additional masks or processes. (Image Omitted) The disclosed process involves diffusing an N-type dopant, e.g., phosphorus, into the trench polysilicon at the same time that the reach-through collector contact is formed. The P-type polysilicon in the trench is thus converted to N-type, producing about a 1-volt shift in the work function differential between the trench polysilicon and the base of the PNP transistor, while also gaining an orders-of- magnitude reduction in leakage. Figs.

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Trench Butted Lateral PNP Transistor

This article concerns a process for making a deep trench butted-free lateral PNP transistor (LPNP) having much lower parasitic PFET channel current than a conventional device employing polysilicon-filled deep trench isolation. The disclosed device can be made on a conventional NPN process line without need of additional masks or processes.

(Image Omitted)

The disclosed process involves diffusing an N-type dopant, e.g., phosphorus, into the trench polysilicon at the same time that the reach-through collector contact is formed. The P-type polysilicon in the trench is thus converted to N- type, producing about a 1-volt shift in the work function differential between the trench polysilicon and the base of the PNP transistor, while also gaining an orders-of- magnitude reduction in leakage. Figs. 1A, 1B and 1C shows a trench- butted LPNP transistor. The process starts with a P-type substrate 1, N+ subcollector diffusion 2, N-type epitaxial 3, a deep trench isolation with dielectric sidewall 4, filled completely to the top with P-type polysilicon 5. During the Nreach-through process, in addition to opening the normal window 6, which serves as the base contact of the LPNP, the window 7 is opened inside the trench around the LPNP, and all the way to a substrate pad (not shown). The N+ poly 17 is then deposited through window 7 in Fig. 1A. Then follows a P-type resistor implant 8 for the emitter and the collector of the LPNP, and the rest of the regular NPN processes, oxide layer 27 is deposited with contact windows 6, 16 and 26 formed later. The N+ implant 7 in the trench around the LPNP makes the Vt of the parasitic PFET more negative. Expected improvement in Vt is...