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Reprioritizing STORES With Respect to GUESSED TAKEN I-Fetches to Improve I-Fetching During TAKEN Branch Delays

IP.com Disclosure Number: IPCOM000034325D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

By reprioritizing STORES from a previous branch-taken-group (BTG), whose putaway falls in a GUESSED-TAKEN interval, the processor design assures that both the taken branch delay is not lengthened and the requisite I-Fetch is interfered with on a minimal basis. The ability to perform the requisite I-Fetching for a BTG is generally limited to the interval between taken branches. Store activity from the previous group can prevent the three initial I-Fetches for the BTG from occurring within the GUESSED-TAKEN interval. With the exception of the dynamics introduced by cache misses and the action and target changes of branches, the inevitability of the I-Fetch-Store interaction is evident. Not only will the store interfere with the I-Fetching, but will continue to do so in a recurrent manner.

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Reprioritizing STORES With Respect to GUESSED TAKEN I-Fetches to Improve I-Fetching During TAKEN Branch Delays

By reprioritizing STORES from a previous branch-taken-group (BTG), whose putaway falls in a GUESSED-TAKEN interval, the processor design assures that both the taken branch delay is not lengthened and the requisite I-Fetch is interfered with on a minimal basis. The ability to perform the requisite I-Fetching for a BTG is generally limited to the interval between taken branches. Store activity from the previous group can prevent the three initial I-Fetches for the BTG from occurring within the GUESSED-TAKEN interval. With the exception of the dynamics introduced by cache misses and the action and target changes of branches, the inevitability of the I-Fetch-Store interaction is evident. Not only will the store interfere with the I-Fetching, but will continue to do so in a recurrent manner. Therefore, the manner of interaction is studied in this concept to determine if modifications of the sequence can improve performance. In certain computer operations, the interaction between fetching and stores is exacerbated by the property that a store can hold off a concurrent fetch for two cycles. The first cycle involving a contention for the cache bus wherein the store is given a priority and in the second cycle the data arrays are unavailable, due to the required separation of directory lookup and data putaway with respect to stores. This is in contra-distinction to fetches where concurrency directory lookup and data access is permitted. To partially alleviate this problem, the cache arrays can be interleaved on a double-word basis, so as to allow those fetches directed to the alternate bank to be processed concurrently with the array putaway action. It is significant to note that in the I-Fetch STORE interaction, the three I-Fetches associated with the taken branch delay are sequential and there is always one, other than the first, whose data access can be overlapped with a store putaway in an interleaved cache. To characterize the problem involved, a notation can be deve...