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Improving Operational Performance of Cache Memories - Execution Tracing

IP.com Disclosure Number: IPCOM000034328D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Doner, DF: AUTHOR [+7]

Abstract

A technique is described whereby internal state information, such as translation lookaside buffers (TLBs), cache directories, branch history tables and other registers, used to retain data not normally visible to the software, can be employed to trace past execution. The concept is considered useful in software recovery and/or failure analysis, since data in these internal registers and arrays typically record recent processor activity. Generally, high performance processors utilize cache memory devices to retain information about recently referenced storage locations on a line granularity. Also, the TLB retains information about recently referenced virtual and real addresses on a page granularity. A branch history table (BHT) contains much useful information about the recent program flow.

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Improving Operational Performance of Cache Memories - Execution Tracing

A technique is described whereby internal state information, such as translation lookaside buffers (TLBs), cache directories, branch history tables and other registers, used to retain data not normally visible to the software, can be employed to trace past execution. The concept is considered useful in software recovery and/or failure analysis, since data in these internal registers and arrays typically record recent processor activity. Generally, high performance processors utilize cache memory devices to retain information about recently referenced storage locations on a line granularity. Also, the TLB retains information about recently referenced virtual and real addresses on a page granularity. A branch history table (BHT) contains much useful information about the recent program flow. All of this information, if present, is typically not visible to the assembly language programmer and the amount and format of the information will vary from machine to machine. The concept described herein advocates using the maintenance processor, or other available means, to provide information at strategically useful times to the main processor. This will enable the processor to either record, in anticipation of future use, or use the information immediately in software recovery actions, or in writing out diagnostic information (dumps). In a simple form, the concept could be implemented on an existing processor with only modifications to the resident code of the service processor and recovery routines. When the information in the internal table registers is changed, the processor usually has available time (cache and TLB misses take significant time to resolve), so that recording replaced information is possible with little performance impact. It is possible, for example, to keep a much larger record of recently referenced pages, such as a first-in first-out (FIFO) stack, in "bump store" than is retained in a TLB. Extending the recording of information kept in internal tables could greatly enhance the diagnostic power of such data. To illustrate the concept, described is a possible collection of diagnostic information that could be derived with the currently available processors, such as the IBM 3090, and their as...