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High-Speed Packet Switching Using an Auxiliary Tag Pipe

IP.com Disclosure Number: IPCOM000034334D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Chang, PC: AUTHOR [+3]

Abstract

A technique is described whereby high-speed packet switching architecture uses an auxiliary tag pipe to indicate incoming data status so as to provide control of the communication switching process, thereby increasing processing speed. An efficient method of processing information to all hardware processing units is described so as to provide a hardware implementation for switching data frames and packets. The architecture is particularly suitable for implementation of lower layer bit-level protocol and can be applied to higher layer protocol processing. However, because of the high speed and simple implementation properties, the concept is considered ideal for general parallel processing. Telecommunication networks increasingly continue to handle high- speed data streams, so as to provide more advanced functions and services.

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High-Speed Packet Switching Using an Auxiliary Tag Pipe

A technique is described whereby high-speed packet switching architecture uses an auxiliary tag pipe to indicate incoming data status so as to provide control of the communication switching process, thereby increasing processing speed. An efficient method of processing information to all hardware processing units is described so as to provide a hardware implementation for switching data frames and packets. The architecture is particularly suitable for implementation of lower layer bit-level protocol and can be applied to higher layer protocol processing. However, because of the high speed and simple implementation properties, the concept is considered ideal for general parallel processing. Telecommunication networks increasingly continue to handle high- speed data streams, so as to provide more advanced functions and services. In certain prior art, packet switching functions have been processed by means of software. However, limitations in the processing power of processors has become a major obstacle in high- speed packet switching systems. This is because the transmission bandwidth requirements has increased much more rapidly than the available power of the processor. The concept described herein provides implementation of certain functions, in hardware, so as to provide a means of increasing the speed and efficient handling of packet switching. The concept involves the switching of data frames and packets and is referred to as the "tag pipe" approach. The hardware high-speed switching implementation provides a means of enabling some packet switching functions, such as 0-bit deletion, 0-bit stuffing, data link connection identifier (DLCI) swapping, cyclic redundancy code (CRC) checking, and CRC generation. The functions are off-loaded from the central processor to special hardware operational units which are dedicated to perform certain functions. Data streams propagate through a data pipe (frame pipe), which can be implemented by means of a series of shift registers. Each operational unit can obtain data from the data pipe, process the data and then return the results back to the data pipe, based on the operational information in the data defined by the protocol. Since the hardware implementat...