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Hedge Fetch History Table

IP.com Disclosure Number: IPCOM000034336D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

This article describes a technique to suppress hedge fetching in those cases where a performance advantage is identified. In a pipeline processor with a cache access time of two cycles, the major performance inhibitor is associated with taken branches and the instruction fetching associated with these branches. A significant performance improvement is derived from a Decode History Table (DHT) which predicts the action of conditional branches at decode time based on the last action of that branch. However, the contention for the cache port among operand accesses and instruction fetches creates a performance penalty when insufficient instruction fetching has been performed and the processor has no instruction to decode dynamic Instruction Buffer Empty (IBE).

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Hedge Fetch History Table

This article describes a technique to suppress hedge fetching in those cases where a performance advantage is identified. In a pipeline processor with a cache access time of two cycles, the major performance inhibitor is associated with taken branches and the instruction fetching associated with these branches. A significant performance improvement is derived from a Decode History Table (DHT) which predicts the action of conditional branches at decode time based on the last action of that branch. However, the contention for the cache port among operand accesses and instruction fetches creates a performance penalty when insufficient instruction fetching has been performed and the processor has no instruction to decode dynamic Instruction Buffer Empty (IBE). The principle cause of this delay is the hedge fetching performed by the processor in anticipation that the branch action has been mispredicted. Thus, the branch target is fetched after the conditional branch that is untaken is decoded and additional instruction fetching is performed on behalf of a fall- through path after a conditional taken branch is decoded. A two-cycle cache access for pipeline processors that decode and agen instructions in the same cycle creates three instruction fetch opportunities for each guessed taken branch. If the branch prediction were perfect, this amount of I-fetching in conjunction with the elimination of hedge fetching for all untaken branch targets would reduce the delay associated with dynamic IBE almost to zero. To accomplish th...