Browse Prior Art Database

Eight- to Sixteen-Bit Universal Synchronous/Asynchronous Receiver and Transmitter Conversion

IP.com Disclosure Number: IPCOM000034344D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Johnson, WJ: AUTHOR [+2]

Abstract

This article describes a circuit arrangement which converts a single, standard, 8-bit-wide universal synchronous/asynchronous receiver and transmitter (USART) in such a way as to appear to be a 16-bit-wide USART to a 16-bit microprocessor. Large-scale integrated circuits, such as gate arrays, contain an abundance of logic gates. The circuitry required to implement this mechanism can be fitted into left-over logic. This provides the capability of implementing this mechanism without consuming real estate on a card. The drawing shows the basic design of the 8- to 16-bit USART converter. During a write cycle, the 16-bit microprocessor places a 16-bit word on the data bus. The control logic enables the high byte tri-state drivers and provides the control signals to write it into memory.

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Eight- to Sixteen-Bit Universal Synchronous/Asynchronous Receiver and Transmitter Conversion

This article describes a circuit arrangement which converts a single, standard, 8-bit-wide universal synchronous/asynchronous receiver and transmitter (USART) in such a way as to appear to be a 16-bit-wide USART to a 16-bit microprocessor. Large-scale integrated circuits, such as gate arrays, contain an abundance of logic gates. The circuitry required to implement this mechanism can be fitted into left-over logic. This provides the capability of implementing this mechanism without consuming real estate on a card. The drawing shows the basic design of the 8- to 16-bit USART converter. During a write cycle, the 16-bit microprocessor places a 16-bit word on the data bus. The control logic enables the high byte tri-state drivers and provides the control signals to write it into memory. Next, the high byte portion of the 16-bit bus is tri-stated and the low byte tri-state drivers are enabled. The low byte is then written to the USART as soon as the USART has finished transmitting the first byte. During a read cycle, while the address is valid, the read register latches the high byte of the 16-bit word being read from the USART. The control logic and the read tri-state drivers for the low byte are enabled. The 16-bit microprocessor will then wait until both bytes are ready by inserting wait states (READY signal is delayed until the sequence is complete). This mechanism eliminat...