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Digital Demodulator for Quad-Burst Position Error Signal

IP.com Disclosure Number: IPCOM000034356D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Mueller, FE: AUTHOR

Abstract

In conventional disk files which use a quad-burst position error signal (PES), the analog PES from the servo head is demodulated by analog techniques. This article describes a technique which digitizes the PES before demodulation and replaces the analog demodulation hardware with digital hardware. The invention is a direct digital demodulator for quad-burst PES encodement. As shown in Fig. 1, it uses a high-speed flash analog-to-digital conversion (ADC) to convert the filtered high-level modulated signal to numeric data. This numeric data is then multiplied by the clocking signal (+1 or -1) and by the gating signal to compute the area under the waveform of the signal. The numeric result is the PES Primary (P), Quad (Q), and AGC feedback control. A typical PES from the servo head is approximately 3 MHz.

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Digital Demodulator for Quad-Burst Position Error Signal

In conventional disk files which use a quad-burst position error signal (PES), the analog PES from the servo head is demodulated by analog techniques. This article describes a technique which digitizes the PES before demodulation and replaces the analog demodulation hardware with digital hardware. The invention is a direct digital demodulator for quad-burst PES encodement. As shown in Fig. 1, it uses a high-speed flash analog-to-digital conversion (ADC) to convert the filtered high-level modulated signal to numeric data. This numeric data is then multiplied by the clocking signal (+1 or -1) and by the gating signal to compute the area under the waveform of the signal. The numeric result is the PES Primary (P), Quad (Q), and AGC feedback control. A typical PES from the servo head is approximately 3 MHz. If 8 conversions are performed on each half cycle, the conversion rate will be 3 x 8 x 2 = 48 meg. This is well within the range of a 6-bit high- speed flash ADC. Less conversions per half cycle can be used if the ADC has higher resolution. Product demodulation is performed by inverting the negative half cycles, summing the values to determine the area under the waveform, and gating the bursts with a single set of logic and the registers to hold the data between bursts. If the disk drive motor spindle speed is closely controlled by driving the motor from a clock, that same clock may be used in place of the ph...