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Cmos Circuit to Eliminate Unwanted Power Transitions on Signal Lines

IP.com Disclosure Number: IPCOM000034361D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Tretter, LL: AUTHOR

Abstract

A series of circuits is described which eliminates power transitions on signal lines during chip power-up and power-down cycles using depletion FET devices and FET transfer devices. Often, in circuit applications, it is desirable not to respond to control inputs to a chip during a power-up or a power-down cycle. A power cycle is defined as the period of time during which supply voltage to the chip is ramping up to its desired value or ramping down (Image Omitted) to zero volts. During this power cycle the control inputs to a chip become very unstable. Because of this it is desirable to not react to these inputs. For most applications the required operation of the chip during the power-up or power-down cycle is very limited.

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Cmos Circuit to Eliminate Unwanted Power Transitions on Signal Lines

A series of circuits is described which eliminates power transitions on signal lines during chip power-up and power-down cycles using depletion FET devices and FET transfer devices. Often, in circuit applications, it is desirable not to respond to control inputs to a chip during a power-up or a power-down cycle. A power cycle is defined as the period of time during which supply voltage to the chip is ramping up to its desired value or ramping down

(Image Omitted)

to zero volts. During this power cycle the control inputs to a chip become very unstable. Because of this it is desirable to not react to these inputs. For most applications the required operation of the chip during the power-up or power-down cycle is very limited. In the case of many chips, not only do a set of specifications have to be met while the power supply is stable, they must be met while the supply is ramping up or down to a zero value. Because of the very high input resistances for FET devices, the operation of FET circuits can be very unpredictable during the power-up and power-down cycle. Depending on the circuit function and state during the power-down cycle, prediction of the node voltage can be very difficult. Also the length of time the circuit is in the zero power condition can affect the value of the node voltage which, in turn, will affect the value during power up. The family of circuits described hereinafter provides a solution to the above problem. Fig. 1 is a circuit which will disconnect internal circuits of a chip from an incoming line and at the same time control the node voltage going to the internal circuit. There are three inputs and one output from the circuit. The input labeled PA0, (INPUT), is the signal input to the circuit. The two inputs, PB0 and PB1, are the control inputs to the circuit that indicate when the supply voltage is below a certain DC value. Q3, Q4, and Q5 are depletion N-channel FET devices. The typical threshold voltage, VT, for these devices is -2.0 volts. This means that when the gate to source voltage of the devices is zero, the devices will still be turned on. The equation below describes the current through the depletion devices. ID = K'Z(VGS - VT)2 For the above equation ID is the drain current, VGS is the gate to source voltage, K' is a constant independent of the size of the device, and Z is the width to length ratio of the device. For our special case the gate and source of the depletion device is connected together. This means that the gate to source voltage, VGS, is always zero volts. For this special case the above equation becomes, ID = K'Z(O - VT)2 = K'Z(VT)2 For a constant voltage from drain to source, VDS, the depletion devices will look like a simple resistor....