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Error Detection and Correction for 4-Bit-Wide Memories

IP.com Disclosure Number: IPCOM000034363D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 6 page(s) / 230K

Publishing Venue

IBM

Related People

Dennis, CA: AUTHOR

Abstract

A novel code design is shown which detects and corrects the highest probable 4-bit-wide memory errors. Error detection and correction (EDC) is used to improve the effective reliability of a memory by detecting and correcting the most (Image Omitted) probable errors. Single bit Hamming EDC codes correct single-bit errors and can detect, without correcting, double-bit errors when an overall parity bit is appended to the word in storage. The predominate error mode for 1-bit wide memory chips is a soft or hard error in a single cell of a word in the storage array or a bit line failure. The next most likely error mode is due to an addressing error on the chip, a word line failure or a power failure on the chip. Both error modes manifest themselves as a single bit error.

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Error Detection and Correction for 4-Bit-Wide Memories

A novel code design is shown which detects and corrects the highest probable 4-bit-wide memory errors. Error detection and correction (EDC) is used to improve the effective reliability of a memory by detecting and correcting the most

(Image Omitted)

probable errors. Single bit Hamming EDC codes correct single-bit errors and can detect, without correcting, double-bit errors when an overall parity bit is appended to the word in storage.

The predominate error mode for 1-bit wide memory chips is a soft or hard error in a single cell of a word in the storage array or a bit line failure. The next most likely error mode is due to an addressing error on the chip, a word line failure or a power failure on the chip. Both error modes manifest themselves as a single bit error. In 4-bit-wide memories, only the first error mode necessarily manifests itself as a single-bit error. The second error mode (global chip error) manifests itself as 0 to 4 bits in error in the fetched word. A novel code is shown which provides effective EDC for both error modes in a 4-bit-wide memory organization, specifically for memories organized up to 60-bit words. By dividing the 60-bit data word to be stored by two polynomials, i.e., x4 + x3 + 1 and x4 + 1, a remainder of 4 bits resulting from each divide, a total of 8 new bits (designated as Gm and Bm), are appended to the word written into memory (Fig. 1a). Subsequently, the data portion of the word fetched from memory is divided by the same two polynomials and the resultant 4-bit remainders are exclusive-ORed with the values Gm and Bm contained in the word fetched. The results, G and B syndrome (Gs & Bs), are used to determine if a detectable error has occurred and what corrections, if any, are necessary (Fig. 1b).

(Image Omitted)

The correction format is as follows:

1) Bs = 0, Gs = 0 No error. (No correction).

2) Bs = 0, Gs is not 0 Gm in error. (No correction).

3) Bs is not 0, Gs = 0 Bs in error. (No correction).

4) Bs is not 0, Gs is not 0 Error in data word.(Correction).

The code-generating matrix for the first error mode is shown in Fig.
2. Labeling the rows with the bit numbers of the data portion of a word (0 to 59), the right four columns indicate how to generate each bit of the Gm character. A particular column in the matrix, i.e., (G0 - G3), is dedicated to each bit in the Gm character. A one in a row indicates that the corresponding data bit is to be included in a binary sum. A binary sum of a set of bits is performed by exclusive-ORing together all bits in the set, i.e., a value for G0 is formed by exclusive-ORing together data bits 0, 4, 7, 8, 10, 12, 13, 14, 15, 19, 22, 23, 25, 27, 28, 29, 30, 34, 37, 38, 40, 42, 43, 44, 45, 49, 52, 53, 55, 57, 58...