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Method of Two-Valued Logic Reduction for Producing Correct Three- Valued Logic Results

IP.com Disclosure Number: IPCOM000034369D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Scheili-Arasi, M: AUTHOR

Abstract

A method of predicting correct result for three-valued logic on digital system simulators is described. Digital System Simulators model digital circuits like the one shown in Fig. 1. The simulator generates the correct output for a given combination of inputs for a certain time interval. Most often a truth table is given, and the simulator generates the minimal reduction and produces the outputs from the reduced equation. Karnaugh maps are commonly used to reduce the truth table. However, because of timing constraints, there is often a possibility of x (unknown), 0 or 1 inputs being present at the inputs to the gates. The reduced outputs of the Karnaugh map in some cases will not produce correct results for three-valued (0,1,x) logic.

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Method of Two-Valued Logic Reduction for Producing Correct Three- Valued Logic Results

A method of predicting correct result for three-valued logic on digital system simulators is described. Digital System Simulators model digital circuits like the one shown in Fig. 1. The simulator generates the correct output for a given combination of inputs for a certain time interval. Most often a truth table is given, and the simulator generates the minimal reduction and produces the outputs from the reduced equation. Karnaugh maps are commonly used to reduce the truth table. However, because of timing constraints, there is often a possibility of x (unknown), 0 or 1 inputs being present at the inputs to the gates. The reduced outputs of the Karnaugh map in some cases will not produce correct results for three-valued (0,1,x) logic. Special considerations have to be made in reducing such binary logic so that the results would be correct in case of three-valued logic.

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An example follows, referring to the truth table shown in Fig. 2, for finding the two- and three-valued reductions. Fig. 3 is a three-valued truth table, with the corresponding three- valued OUT and also the result for OUT(2) for three-valued inputs. The reason for the incorrect result, is in the way the Karnaugh map is reduced. For two-valued logic input, the minimal reduction would work perfectly. However, the resulting equation would produce incorrect results in most cases for three-valued logi...