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Charge Amplifying Dynamic Random Access Memory Cell Operation in the Two-Volt Range

IP.com Disclosure Number: IPCOM000034400D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Kenney, DM: AUTHOR [+2]

Abstract

Two techniques are described which provide good signal level from charge amplifying dynamic random access memory (DRAM) cells operated at two volts or less to preserve reliability of thin gate oxide. One technique is to operate the cell with pushed plate or storage node boosted. The other technique uses a modified charge amplifying cell having an added transistor, also operated with the pushed plate or boosted word line, providing capability to locally refresh storage node charge. (Image Omitted) Fig. 1 is a schematic of the charge amplifying DRAM cell (CACELL). Transistor T1 and T2 are P-channel field-effect transistors (FETs) having threshold voltage Vt = -2 volts for T1 and Vt = -1 volt for T2. Coupling ratio of node C to node RD (read line) is 2/3, i.e., a 3 volt transition on node RD causes a 2 volt change on node C.

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Charge Amplifying Dynamic Random Access Memory Cell Operation in the Two-Volt Range

Two techniques are described which provide good signal level from charge amplifying dynamic random access memory (DRAM) cells operated at two volts or less to preserve reliability of thin gate oxide. One technique is to operate the cell with pushed plate or storage node boosted. The other technique uses a modified charge amplifying cell having an added transistor, also operated with the pushed plate or boosted word line, providing capability to locally refresh storage node charge.

(Image Omitted)

Fig. 1 is a schematic of the charge amplifying DRAM cell (CACELL). Transistor T1 and T2 are P-channel field-effect transistors (FETs) having threshold voltage Vt = -2 volts for T1 and Vt = -1 volt for T2. Coupling ratio of node C to node RD (read line) is 2/3, i.e., a 3 volt transition on node RD causes a 2 volt change on node C. Node BL is the bit line and node WL is the word line. A storage capacitor is shown connected from node C to node RD. Refresh and Standby (starting from Standby region 1 of Fig. 2): Read line RD pulses to ground (0.0 volts) in region 2 of the timing diagram of Fig. 2. If node C contains high data, transistor T1 does not conduct. If node C contains "low" voltage (data), transistor T1 conducts and the bit line begins to discharge. When adequate signal is on the bit line, the bit line sensing circuits complete setting the "low" bit line to 0.0 volts. The word line WL is pulsed to 0.0 volts at the beginning of timing chart region 3, the time period in which low cells are written back. RD pulses to 3 volts and the "low" voltage is re-written into node C from the bit lines. Node C reaches a +1 volt level. If node C contained "high" voltage (data), then node C is at 2 volts, as shown at the beginning of timing chart region 4, the time period during which high cells are written back. Read line RD pulses to 2 volts. Node C couples to 0.3 volts or remains at 2 volts depending on data on the bit lines. The "high" cell voltage is now charged to 2 volts from the 2 volt bit line. The word line returns to 2 volts followed by RD returning to 3 volts, as shown in timing region 5. Then the bit lines are all returned to 2 volts. All nodes are then at "standby" levels, as shown in region 6 of the timing chart of Fig. 2. Read: Read line RD pulses to ground (0.0 volts). The read does not destroy the charge on node C. RD is returned to 3 volts and then all bit lines are returned to 2 volts. The cell is then back in standby. Write: The write cycle is identical to a refresh cycle with the bit lines forced to over-write the previous data i...