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Fixed Pulse Width Phase Correction Logic for Digital Phase-Locked Loop

IP.com Disclosure Number: IPCOM000034408D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Bui, NX: AUTHOR

Abstract

This article describes a technique for using a digital phase-locked loop having a fixed pulse-width single-shot pulse for correcting phase error in a variable control oscillator when there is no data pulse to lock on to. The previous circuits used in the art solved the problem of obtaining phase lock where data pulses were missing, by locking to the falling edge of each existing data pulse and providing a single-shot pulse width that varied such that it would equal and track to the varying VCO pulse width. However, it is difficult to design an integrated circuit logic a single shot having a pulse width which has to vary and the logic necessary to have the pulse width tracked to another varying pulse width. (Image Omitted) The present circuit illustrated in Fig. 1, enables a phase arrangement such as that as illustrated in Fig.

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Fixed Pulse Width Phase Correction Logic for Digital Phase-Locked Loop

This article describes a technique for using a digital phase-locked loop having a fixed pulse-width single-shot pulse for correcting phase error in a variable control oscillator when there is no data pulse to lock on to. The previous circuits used in the art solved the problem of obtaining phase lock where data pulses were missing, by locking to the falling edge of each existing data pulse and providing a single-shot pulse width that varied such that it would equal and track to the varying VCO pulse width. However, it is difficult to design an integrated circuit logic a single shot having a pulse width which has to vary and the logic necessary to have the pulse width tracked to another varying pulse width.

(Image Omitted)

The present circuit illustrated in Fig. 1, enables a phase arrangement such as that as illustrated in Fig. 2, which overcomes the need for a variable single-shot pulse circuit. Basic to the configuration is the use of a variable control oscillator single shot which is triggered by the rising edge of the variable control oscillator pulse and has a width equal to the data pulse width. The falling edge of this variable control oscillator single-shot signal is then phase locked with the falling edge of the data pulse. Since both pulses have the same width, there rising edges line up during lock condition in the phase-locked loop. Since the variable control oscillator single-shot...