Browse Prior Art Database

L2 Latch With Post Indication

IP.com Disclosure Number: IPCOM000034409D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 77K

Publishing Venue

IBM

Related People

Maley, GA: AUTHOR [+2]

Abstract

This article concerns the design of a post indicating latch (L2) circuit, having two different outputs, which can be employed to effectively eliminate a "short path" problem commonly encountered when optimizing the performance of large systems designed to the double register (L1/L2) concept. (Image Omitted) A typical double register (L1/L2) design is shown in Fig. 1. Overlapping the critical edges of the C1 and C2 clocks will act to increase system performance by decreasing cycle time but can result in a potential "short path" problem for some data paths. This design restraint occurs when a signal launched from an L2 latch catches up with data from the previous cycle by passing through a very short logic path in the combinational logic, thereby destroying the earlier data.

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L2 Latch With Post Indication

This article concerns the design of a post indicating latch (L2) circuit, having two different outputs, which can be employed to effectively eliminate a "short path" problem commonly encountered when optimizing the performance of large systems designed to the double register (L1/L2) concept.

(Image Omitted)

A typical double register (L1/L2) design is shown in Fig. 1. Overlapping the critical edges of the C1 and C2 clocks will act to increase system performance by decreasing cycle time but can result in a potential "short path" problem for some data paths. This design restraint occurs when a signal launched from an L2 latch catches up with data from the previous cycle by passing through a very short logic path in the combinational logic, thereby destroying the earlier data. Delay pads (time delay circuit elements) are normally inserted in the "short paths" to overcome this problem but require additional power and chip area to assure that the data arrives at the L1 latch after the C1 clock has turned off. Fig. 2 shows a CSEF (current switch emitter follower) L2 latch circuit with post indication which uses less chip area and power to obtain the desired result. The disclosed latch circuit design includes, in addition to the usual hazard free output Q, a second output Qp that is post indicating. Post indicating means that the data does not change until the clock falls, thereby eliminating the need for delay pads since, when clock C2 fall...