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Scheme of Array Test Latch

IP.com Disclosure Number: IPCOM000034420D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Shen, MN: AUTHOR

Abstract

Extremely accurate and balanced clock timings of high performance embedded arrays can be measured using the subject test latch. Referring to Fig. 1, a test latch is used between the array and the driver to latch the output data before going to the driver. An array data output signal can be used to set the latch and an external test clock signal can be used to prevent the latch from changing. The external test clock signal is connected in parallel through and-inverter logic gates AI1 and gates AI2 and AI3. AI1 is connected to the test latch enable T1 and AI3 is connected to test latch clock CLK. The rising edge of AI1 is now faster than the rising edge of AI3 thus balancing the output of the test latch independent of the initial start-up data input to the test latch.

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Scheme of Array Test Latch

Extremely accurate and balanced clock timings of high performance embedded arrays can be measured using the subject test latch. Referring to Fig. 1, a test latch is used between the array and the driver to latch the output data before going to the driver. An array data output signal can be used to set the latch and an external test clock signal can be used to prevent the latch from changing. The external test clock signal is connected in parallel through and-inverter logic gates AI1 and gates AI2 and AI3. AI1 is connected to the test latch enable T1 and AI3 is connected to test latch clock CLK. The rising edge of AI1 is now faster than the rising edge of AI3 thus balancing the output of the test latch independent of the initial start-up data input to the test latch. AI4 is added between the test latch and test driver and gated by positive (+) test output of the array. This permits the system logic to run the test while in system mode. Now, if the array data output signal occurs before the specified clock reset signal, then the access time is acceptable and the delay of the array is accurately determined.

(Image Omitted)

From Fig. 2, the operation of the test latch can be determined as follows: When the latch enable signal is a "0", transistor T1 of Fig. 2 is turned on. T3 is kept off, and the latch is disabled. When the enable signal is a "1", T1 is off and the latch is in the enable mode. During the enable mode, the test clock signal i...