Browse Prior Art Database

Digital Signal Processing

IP.com Disclosure Number: IPCOM000034422D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Locke, ME: AUTHOR

Abstract

A signal power limiter for restrictively filtering digital signals to conform with FCC signal output regulations is described. The signal power limiter is implemented as a nonlinear feedback loop, as shown in the figure. 1. The signal is accumulated and initialized to zero at time zero. Then, the signal is divided by a scale factor at function block 30 and exponentiated at function block 40. The result is multiplied by input signal X to form the output Y. Y is fed back into the loop at 10 by squaring the signal Y, subtracting the power limit at 11 and adding the resultant to the accumulator at 12. Then, any negative results are set to zero at 20, and the result is stored in an accumulator register 25. The target output signal power limit is adjusted to conform with requirements by adjusting the power limit 11.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 88% of the total text.

Page 1 of 2

Digital Signal Processing

A signal power limiter for restrictively filtering digital signals to conform with FCC signal output regulations is described. The signal power limiter is implemented as a nonlinear feedback loop, as shown in the figure. 1. The signal is accumulated and initialized to zero at time zero. Then, the signal is divided by a scale factor at function block 30 and exponentiated at function block 40. The result is multiplied by input signal X to form the output Y. Y is fed back into the loop at 10 by squaring the signal Y, subtracting the power limit at 11 and adding the resultant to the accumulator at 12. Then, any negative results are set to zero at 20, and the result is stored in an accumulator register 25. The target output signal power limit is adjusted to conform with requirements by adjusting the power limit 11. The scale factor 30 is a time constant that changes the amount of time necessary for the algorithm to respond. The accumulator is limited to positive values to keep signal levels that are less than the power limit from being amplified. The result is that the signal power accumulator increases if Y2 is greater than the target output signal power limit, and decreases otherwise. If the signal power accumulator increases 2 -A/C, decreases, generally causing Y to become smaller (C = time constant in function block 30 and A = value in function block
25). The circuitry slowly reduces the power of signals that are slightly above the power...