Browse Prior Art Database

Operator Panel DATA Serializer Circuit

IP.com Disclosure Number: IPCOM000034428D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 68K

Publishing Venue

IBM

Related People

Knepper, LE: AUTHOR

Abstract

A technique is described whereby an operator panel data serializer circuit provides a means of generating minicomputer data messages, without extensive central processing unit (CPU) overhead and without machine speed dependency. The concept is an improvement designed to increase processing speed. Typically, a minicomputer, such as the IBM System 88, will send messages (commands and data characters) to a sixteen-character display by means of a signal line that doubles as the "serial data" line. The command and data bytes are encoded as an asynchronous 16-bit message unit with the following format: 1 1 1 0 D0 D1 D2 D3 D4 D5 D6 D7 A0 0 1 1 [[[ [[[ [[[[[[[[[[[[[[ [[[[[[[[[[[[[[[ [[ [[ Header Command or Data Byte Trailer where A0 = 1 for data, A0 = 0 for commands.

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Operator Panel DATA Serializer Circuit

A technique is described whereby an operator panel data serializer circuit provides a means of generating minicomputer data messages, without extensive central processing unit (CPU) overhead and without machine speed dependency. The concept is an improvement designed to increase processing speed. Typically, a minicomputer, such as the IBM System 88, will send messages (commands and data characters) to a sixteen-character display by means of a signal line that doubles as the "serial data" line. The command and data bytes are encoded as an asynchronous 16-bit message unit with the following format: 1 1 1 0 D0 D1 D2 D3 D4 D5 D6 D7 A0 0 1 1 [[[ [[[ [[[[[[[[[[[[[[ [[[[[[[[[[[[[[[ [[ [[ Header Command or Data Byte Trailer where A0 = 1 for data, A0 = 0 for commands. A logic "1" is a positive edge which persists for longer than a sixteen microsecond pulse width. A logic "0" is a positive edge wherein the pulse width is less than sixteen microseconds. In the prior-art circuitry, in order to generate a message unit, the CPU must turn a latch on and off, in the display signal line, in the proper sequence and for the proper duration. For example, assuming an average of an equal number of "1" (greater than 16 msec.) and "0" (less than 16 msec.) pulses, a 16-bit message will require 16 x 16 = 256 msec. of dedicated CPU time for each message unit. A complete message on the display will require up to sixteen message units, plus several commands, indicating a significant overhead requirement. In addition, the definition of a "0" and a "1" must be such that, when operating any one of the minicomputer models, the same code will result in the message unit for proper interpretation. For example, a "0" must be chosen such that the same code provides a pulse lasting less than 16 usec. on all models and similarly for a "1". The concept described herein consists of a circuit, as shown in Fig. 1, which provides the following: - Provide...