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Programmable Memory Controller

IP.com Disclosure Number: IPCOM000034430D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 4 page(s) / 117K

Publishing Venue

IBM

Related People

Quach, BS: AUTHOR [+2]

Abstract

A technique is described whereby a programmable memory controller (PMC) provides a design support means to rapidly implement high speed dynamic memory devices into computer designs. The PMC provides the design support by enabling a designer to alter processor-memory timing relationships through the use of microcode so that design changes and upgrades to memory circuitry can rapidly be made by simply altering a memory initialization table. During computer product development cycles, faster and denser dynamic random-access memory (RAM) devices become available which have a tendency to obsolete predecessor RAM chips. A designer, using the faster chips, must make extensive design changes, often requiring a new product design cycle, to implement the advanced memory in the memory circuitry.

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Programmable Memory Controller

A technique is described whereby a programmable memory controller (PMC) provides a design support means to rapidly implement high speed dynamic memory devices into computer designs. The PMC provides the design support by enabling a designer to alter processor-memory timing relationships through the use of microcode so that design changes and upgrades to memory circuitry can rapidly be made by simply altering a memory initialization table. During computer product development cycles, faster and denser dynamic random-access memory (RAM) devices become available which have a tendency to obsolete predecessor RAM chips. A designer, using the faster chips, must make extensive design changes, often requiring a new product design cycle, to implement the advanced memory in the memory circuitry. The concept described herein provides a method whereby the designer need only re-program the circuitry involved in order to be able to accept a new memory technology. The only hardware changes would be a new read-only memory (ROM) for configuring and testing the additional memory and a new circuit layout to accept the new RAM modules because of different pin configurations. The PMC consists of three basic components: 1) A Critical Timing Control Signal Generator - Allows the

circuit designer to program processor-memory timings for

each memory interface signal.

(Image Omitted)

2) A Programmable Address Multiplexer - Allows the circuit

designer to program the width of the RAM multiplexed

address bus.

3) A Programmable/Variable Refresh Timer - Allows the

designer to compensate for variations in refresh rates

of the various memory devices.

(Image Omitted)

The critical timing control signal generator is composed of delay line 10, as shown in Fig. 1, delay line selector 11 and register 12, which is used to retain the programmed delay value. The generator enables the designer to define the time between critical timing points, such as the delay between memory timings. A critical timing point may require more than one critical timing control signal generator. The programmable address multiplexer consist of a series of 4 to 1 data selects for address control, 2 to 1 data selectors for RAM control, refresh control logic unit 13, as shown in Fig. 2, and refresh timer address counter 14. The physical width of this bus is A0 - A10, so as to allow memory modules that can a...