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Automatic Testing Circuit for Combinational Logic

IP.com Disclosure Number: IPCOM000034441D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Millas, RJ: AUTHOR [+4]

Abstract

A technique is described whereby a test circuit is added to level- sensitive scan design (LSSD) circuitry so as to provide a means to automatically test combinational logic which feeds input data to random-access memory (RAM) macros. The circuit eliminates the need to functionally test out scanning values through LSSD scan strings. Software can now be generated to provide a means to statically test the function. In prior art, testing of combinational logic circuitry required a functional testing procedure which required toggling the primary inputs with a tester to scan out the values through the LSSD scan strings. When a RAM macro is imbedded within a module, together with other logic, it becomes difficult to test the combinational logic feeding the inputs of the RAM macro.

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Automatic Testing Circuit for Combinational Logic

A technique is described whereby a test circuit is added to level- sensitive scan design (LSSD) circuitry so as to provide a means to automatically test combinational logic which feeds input data to random-access memory (RAM) macros. The circuit eliminates the need to functionally test out scanning values through LSSD scan strings. Software can now be generated to provide a means to statically test the function. In prior art, testing of combinational logic circuitry required a functional testing procedure which required toggling the primary inputs with a tester to scan out the values through the LSSD scan strings. When a RAM macro is imbedded within a module, together with other logic, it becomes difficult to test the combinational logic feeding the inputs of the RAM macro. To overcome this difficulty, the concept provides a circuit configuration so that software can automatically test combinational logic. Two specific applications are discussed: multiple combinational logic inputs; and when an asynchronous input precedes the combinational logic.

(Image Omitted)

In the multiple combinational logic application, the circuit is designed so that all the inputs are ORed together at OR module 10, shown in Fig. 1. After the ORing, the signals are latched by means of testability latch module 11, which is used only during the testing phase. The output of latch 11 feeds no other logic, except to the scan string circuitry. U...