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Unified Simulation Using Flow Tables

IP.com Disclosure Number: IPCOM000034442D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Ditlow, GS: AUTHOR

Abstract

There are predominantly two classes of simulators in use today -- switch level [1] and gate level [2]. When simulating chips or large macros, a gate level representation is preferable for performance reasons since the simulation time is an order of magnitude faster than with a switch level representation. However, previous gate level representations have modeled Boolean behavior only and not the non-Boolean behavior of pass transistors [3]. Described here is a generalized gate level simulator which uniformly simulates both gate level and switch level designs. This is accomplished by creating "flow tables" [4] from the design. Flow tables model the sequential behavior in precharged and charge sharing FET circuits. They are also useful in the analysis of latches implemented with gates.

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Unified Simulation Using Flow Tables

There are predominantly two classes of simulators in use today -- switch level [1] and gate level [2]. When simulating chips or large macros, a gate level representation is preferable for performance reasons since the simulation time is an order of magnitude faster than with a switch level representation. However, previous gate level representations have modeled Boolean behavior only and not the non-Boolean behavior of pass transistors [3]. Described here is a generalized gate level simulator which uniformly simulates both gate level and switch level designs. This is accomplished by creating "flow tables" [4] from the design. Flow tables model the sequential behavior in precharged and charge sharing FET circuits. They are also useful in the analysis of latches implemented with gates. Combinational circuits are a special case of flow tables where no feedback exists. A detailed description of the techniques used to implement a generalized gate level simulator are described in [5, 6]. Advantages There are several reasons why this approach improves simulation performance: $ Gate level descriptions are at a higher level than

switch level descriptions. Since an order of

magnitude fewer components are used, the

simulation is faster. In addition, the

interpretive overhead inherent in switch level

simulation is eliminated.

$ Gate level descriptions are a compiled

representation of FET networks. It is usually

worth the additional compilation time so that

large regression simulations are possible.

$ Hardware accelerators like the LSM, EVE, and EVE2

use gates as their simulation primitives. There

have been attempts at encoding switch level

simulators into EVE hardware...