Browse Prior Art Database

Microprocessor Bus State Monitor System

IP.com Disclosure Number: IPCOM000034447D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 5 page(s) / 95K

Publishing Venue

IBM

Related People

Begun, RM: AUTHOR [+4]

Abstract

This article describes a tool for debug and testing of a microprocessor system using a test tool that operates in the I/O channel rather than replacing the system CPU. The bus state monitor system (BSMS) is a tool designed for debug and testing of a microprocessor system. The BSMS is a departure from traditional development systems that are used. Such processor replacement systems require that the processor be replaced by a special module that is attached to the development system and is inserted in place of the processor chip. The BSMS, however, interfaces to the system under test (SUT), through the low end parallel bus (LEPB) I/O channel without replacing the processor. Thus, the final system configuration is tested with a processor installed versus a replacement probe.

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Microprocessor Bus State Monitor System

This article describes a tool for debug and testing of a microprocessor system using a test tool that operates in the I/O channel rather than replacing the system CPU. The bus state monitor system (BSMS) is a tool designed for debug and testing of a microprocessor system. The BSMS is a departure from traditional development systems that are used. Such processor replacement systems require that the processor be replaced by a special module that is attached to the development system and is inserted in place of the processor chip. The BSMS, however, interfaces to the system under test (SUT), through the low end parallel bus (LEPB) I/O channel without replacing the processor. Thus, the final system configuration is tested with a processor installed versus a replacement probe. This eliminates problems that have occurred when using processor replacement systems that affect bus and interface timings. It also provides more information and functions for hardware development than is available on processor replacement systems.

(Image Omitted)

Operationally, the BSMS requires two systems, as illustrated in block diagram in Fig. 1. The first one is the SUT, which is the system that is being tested. The BSMS card resides in this system. The second system (the monitor) is a personal computer (PC) that contains a modified parallel card and is connected to the SUT through an interface cable. The user of this system controls the SUT by use of a program that resides in the system. Data and commands are communicated from the BSMS to the SUT through the cable.

(Image Omitted)

The BSMS card hardware is shown in block diagram in Fig. 2. The hardware interface to the SUT is provided by the BSMS card that plugs into a 32-bit I/O channel slot in the SUT. It provides the following capabilities: oLatch system 32-bit address. The 32-bit address bus latches

are used to transfer the system address to the monitor via

the parallel port.

o Receive system 32-bit data. The 32-bit data bus transceivers

are gated out to the monitor system via the parallel port.

oReceive and monitor system control bus signals. The control

bus latches and receivers are used to transfer system

information through the parallel port.

oDrive I/O channel ready when requested by the monitor. The

single-step control timing circuits drive the I/O channel

ready signal to the SUT either in the signal step mode or

breakpoint mode, as requested by the monitor system.

o Set and control address and cycle-type breakpoints. The bus state monitor logic contains address and cycle-type comparators.

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These comparators are preset by the monitor system via the parallel port. When the preset breakpoint appears on the system bus, the comparators trigger the single-step control timing circuit which drives I/O channel ready onto the system bus. Except for the I/O Channel Ready signal, the card is completely passive in the SUT. When requested by the monitor pro...