Browse Prior Art Database

Output Timing Measurement in Physical Modeling

IP.com Disclosure Number: IPCOM000034458D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Robinson, SG: AUTHOR

Abstract

Disclosed is a method for precisely measuring logic signal output timings from a real hardware device. A very similar technique can be used to precisely stimulate logic signal inputs or bidirectional signals. These precise timings are used in a logic simulator to verify the logic design or in a fault simulator to generate functional speed test data. The advantages of the disclosed method is accuracy and performance. Theoretically, the accuracy can be that of one primitive gate delay in the pin electronics integrated circuit. Simulation performance impact is negligible. A minimal embodiment employs logic enhancements to the typical pin electronics.

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Output Timing Measurement in Physical Modeling

Disclosed is a method for precisely measuring logic signal output timings from a real hardware device. A very similar technique can be used to precisely stimulate logic signal inputs or bidirectional signals. These precise timings are used in a logic simulator to verify the logic design or in a fault simulator to generate functional speed test data. The advantages of the disclosed method is accuracy and performance. Theoretically, the accuracy can be that of one primitive gate delay in the pin electronics integrated circuit. Simulation performance impact is negligible. A minimal embodiment employs logic enhancements to the typical pin electronics. These logic enhancements consist of a change state detector circuit, a coarse delay counter circuit, various delay circuits, a primitive gate propagation delay counter, and a delay holding register circuit.

Refer to the figure. The coarse delay counter circuit is started at some reference time (e.g., simulation start time or an input signal change). This start reference signal causes the delay counters and the holding register to reset. When the change state detector detects a change, the coarse delay counter circuit count and primitive gate propagation delay counter value is transferred to the delay holding register circuit which the simulator may access. The fundamental objective is to measure the coarse delay time with counters and append a fine delay time of primitive g...