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DRAM Current Gain Cell With Local Refresh

IP.com Disclosure Number: IPCOM000034461D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Busch, RE: AUTHOR [+4]

Abstract

A dynamic random access memory (DRAM) cell with local refresh between cycles is reported. The cell offers nearly 100% availability, low power consumption and charge amplification. Dynamic random access memory cells store charge on capacitors through an access transistor. Charge leaks off in time and must be periodically replaced. During the cell charge replacement interval (refresh) the DRAM chip may not be read or write accessed and the time lost results in an availability problem, degrading system performance. Providing a charge amplifying cell with local refresh capability results in a cell design nearly equivalent to a static random access memory (RAM) cell and requires much less silicon area for each cell. A schematic of the charge amplifying DRAM cell with local refresh is shown in Fig. 1.

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DRAM Current Gain Cell With Local Refresh

A dynamic random access memory (DRAM) cell with local refresh between cycles is reported. The cell offers nearly 100% availability, low power consumption and charge amplification. Dynamic random access memory cells store charge on capacitors through an access transistor. Charge leaks off in time and must be periodically replaced. During the cell charge replacement interval (refresh) the DRAM chip may not be read or write accessed and the time lost results in an availability problem, degrading system performance. Providing a charge amplifying cell with local refresh capability results in a cell design nearly equivalent to a static random access memory (RAM) cell and requires much less silicon area for each cell. A schematic of the charge amplifying DRAM cell with local refresh is shown in Fig. 1. Transistors T1, T2 and T4 with capacitor C1 is the charge amplifying cell with node A as the bit line and T2 is a parasitic transistor. By adding T3 to the cell, the bit line is moved and a separate word line (WL) is added. Also, all transistors for the P- channel cell have thresholds set at - 1 volt except T1 and T2 which are set at -1.5 volts or more. The bit line (BL), word line (WL) and refresh/read (Ref/Rd) line shown in the refresh timing diagram (Fig. 2) are initially set at VDD (3.3 volts +/- 10% or approximately 3.0 to
3.6 volts) and the refresh write (Ref/Wr) line is set at VDD - 1 volt. Nodes A and C are at VDD for high level data and node A < 1 volt and node C = +1 volt for low level data. To refresh a cell storage node, the bit line is held actively to VDD during the refresh cycle. The word line is pulsed to ground, node A charges to VDD (or stays at VDD for high level data) and the word line is returned to VDD. The refresh/read line is pulsed to ground and node C couples in a negative direction to VDD-WV if a high level is stored or from +1 volt to -1 volt if a low level is stored. The ratio of capacitance C1 to node C stray capacitance allows a -2 volt swing on node C if a low level is stored. With a high level stored, T4 is on and the stray capacitance of node A is included with the stray capacitance of node C in the ratio with capacitance C1. With -1 volt on the gate of T1, node A discharges to ground and refresh/read returns to VDD. Node C couples in a positive direction, up to +1 volt or VDD depending upon the data stored in the cell. Refresh/write pulses to ground, turns on T4 and charge is shared between nodes A and C for low level stored data. Note that node A is at ground and if node C had leakage and went more positive than +1 volt, the charge is restored to the +1 level. High level data is restored to VDD when the word line is pulsed to ground as noted earlier. The refresh/write line is returned to VDD-1 volt. (T4 is on for high level d...