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Latch Model Reduction Using Latch Behaviorals

IP.com Disclosure Number: IPCOM000034476D
Original Publication Date: 1989-Feb-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Forlenza, DO: AUTHOR [+5]

Abstract

An algorithm using minimized modelling of circuit latch parameters can be used to reduce CPU time and memory required for simulation and test generation of latches in LSSD (Level Sensitive Scan Design) circuits. The algorithm proposes using a more generalized entity, a latch behavior, to replace the latches in LSSD modelling. The algorithm defines a latch behavioral, as having clock data pairs as inputs, one output and a clock which must be set to a '1' for data to be captured in the latch. In the algorithm, when multiple clocks are activated simultaneously, clock dominance tables will predict the latch output resolution. The figure shows the flow chart of the algorithm. Step 1. Input Function Identification for LSSD Latches Tag blocks are used as part of the logic model.

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Latch Model Reduction Using Latch Behaviorals

An algorithm using minimized modelling of circuit latch parameters can be used to reduce CPU time and memory required for simulation and test generation of latches in LSSD (Level Sensitive Scan Design) circuits. The algorithm proposes using a more generalized entity, a latch behavior, to replace the latches in LSSD modelling. The algorithm defines a latch behavioral, as having clock data pairs as inputs, one output and a clock which must be set to a '1' for data to be captured in the latch. In the algorithm, when multiple clocks are activated simultaneously, clock dominance tables will predict the latch output resolution. The figure shows the flow chart of the algorithm. Step 1. Input Function Identification for LSSD Latches Tag blocks are used as part of the logic model. Tag blocks and the primitive logic blocks comprise what is called the LSSD latch. The tag block functions are used to assist in creating "Latch" block behaviorals. The definition of tag blocks "play" an important role in defining the functional input lines of the LSSD latches. Typically, there are a number of different types of tag blocks. Tag blocks define clock lines, scan-in lines, synchronous set and reset lines. Tag block modelling provides LSSD functional information to the test generation application programs. The inputs of the latch must be known so that each line can be treated according to function. The tracing back from the defined tag block inputs until a boundary is reached is part of the algorithm used. Some identification of boundaries require searching outside the scope of the LSSD latch. The trace-back routine is a general approach. However, since there are many different types of latches, some exceptions are encountered. The exceptions are handled by tracing the LSSD latch, researching Shift Register Latch (SRL) Block Transformation Rules (BT...