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Multiplexed Column Redundancy Method for Complementary Metal Oxide Silicon Memory

IP.com Disclosure Number: IPCOM000034483D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 85K

Publishing Venue

IBM

Related People

Williams, T: AUTHOR

Abstract

This multiplexer logic control circuitry facilitates redundant column substitution for memory arrays. The method is self-timed and operates under control of normal memory chip control pulses. Referring to Fig. 1, a number of array blocks are represented by blocks 4 and 6 each supported by primary data busses 8, 10, 12 and 14; sense amplifiers 16, 18, 20 and 22, and input data drivers 24, 26, 28 and 30. The sense amplifiers 16 and 20 are connected to secondary chip output data bus 32. Sense amplifiers 18 and 22 are connected to secondary chip output data bus 34. Input data drivers 24 and 28 are connected to input data bus 36, and drivers 26 and 30 are connected to (Image Omitted) input data bus 38. A series of redundant multiplexed columns 40 have attached sense amplifiers 42 and 44, and data input drivers 46 and 48.

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Multiplexed Column Redundancy Method for Complementary Metal Oxide Silicon Memory

This multiplexer logic control circuitry facilitates redundant column substitution for memory arrays. The method is self-timed and operates under control of normal memory chip control pulses. Referring to Fig. 1, a number of array blocks are represented by blocks 4 and 6 each supported by primary data busses 8, 10, 12 and 14; sense amplifiers 16, 18, 20 and 22, and input data drivers 24, 26, 28 and 30. The sense amplifiers 16 and 20 are connected to secondary chip output data bus 32. Sense amplifiers 18 and 22 are connected to secondary chip output data bus 34. Input data drivers 24 and 28 are connected to input data bus 36, and drivers 26 and 30 are connected to

(Image Omitted)

input data bus 38. A series of redundant multiplexed columns 40 have attached sense amplifiers 42 and 44, and data input drivers 46 and 48. Substitution of a redundant column from array 40 for a failed column in array 4 or 6 is accomplished with the aid of address fuse comparators 50, decoders 52 and the multiplexer logic control 54. Fuse comparators 50 provide information to the spare bit switch decoders 52, indicating a match between a bad column address and an incoming address. Fuses (not shown) are used to enable the redundant decoders. Redundant operations are synchronized with normal operations by utilizing the same global timing signals which control normal toggle, static column, and page operations. At the occurrence of a match, complementary decoder signals R and S select a redundant column bit switch pair 56 or 57 (identical circuits) and activate multiplexer logic control 54. Fig. 2 is a detailed schematic diagram of the multiplexer logic control block 54 of Fig. 1. This particular imp...