Browse Prior Art Database

Combined PC Tools and Simulation for Early Testing

IP.com Disclosure Number: IPCOM000034494D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 4 page(s) / 96K

Publishing Venue

IBM

Related People

Batalden, GD: AUTHOR [+4]

Abstract

The addition of PC to a Full Function Test System (FFTS) has made it possible to eliminate simulator-only test cases by allowing test cases designed for the real hardware to also be used in the simulated environment. The techniques of this disclosure connected the PC-driven testing with a simulated FFTS and I/O processor (IOP). To show the detail of this unique connection, it is first necessary to more completely define the I/O processor and the model of it. Very simply this I/O processor attaches to the I/O bus. This processor, in turn, attaches physical I/O devices such as hard disks and tape, but it is possible to consider these devices as a part of the IOP. When this "larger" IOP is considered, all input and output is via the bus, as in Fig. 1.

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Combined PC Tools and Simulation for Early Testing

The addition of PC to a Full Function Test System (FFTS) has made it possible to eliminate simulator-only test cases by allowing test cases designed for the real hardware to also be used in the simulated environment. The techniques of this disclosure connected the PC-driven testing with a simulated FFTS and I/O processor (IOP). To show the detail of this unique connection, it is first necessary to more completely define the I/O processor and the model of it. Very simply this I/O processor attaches to the I/O bus. This processor, in turn, attaches physical I/O devices such as hard disks and tape, but it is possible to consider these devices as a part of the IOP. When this "larger" IOP is considered, all input and output is via the bus, as in Fig. 1.

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To allow early debugging of the micro-code the first step was to provide a "traditional" model or simulation. This is really like encapsulating the new IOP somehow in an existing mainframe computer. Inputs and outputs to the IOP are then still over the I/O bus, but it is a simulated bus, as seen in Fig. 2. Two items are key to allowing the unique simulation which developed. First, the FFTS is built around a PC which shares memory with the FFTS processor. Second, the FFTS is in many ways similar to the IOP: both utilize a 68000 processor, the memory accessing is the same, both interface to the I/O bus, and both have similar interrupt structure. An FFTS system connected to an IOP can be represented as shown in Fig. 3. Thus, due to the similarity of the FFTS and the IOP it is possible to use the IOP model to also model the FFTS. Minor changes are required to deal with some FFTS-unique hardware, but the IOP is nearly a superset of the FFTS. Therefore, starting with the IOP simulator it is possible to model the FFTS in a mainframe computer.

(Image Omitted)

To complete the simulation of the FFTS, it is necessary to consider the PC part of the FFTS. As attached to the FFTS, the PC acts both as an independent processor, and an I/O device. The PC is used as an independent processor because a test language...