Browse Prior Art Database

High Performance Printer Adapter

IP.com Disclosure Number: IPCOM000034495D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 116K

Publishing Venue

IBM

Related People

Howell, JH: AUTHOR [+3]

Abstract

A versatile printer host system adapter is constructed by placing a microprocessor, memory and common logic on the same circuit card and using a second card for the specialized circuits to accommodate different physical links to various host processors. (Image Omitted) Fig. 1 illustrates the circuit components of the common card, while Fig. 2 shows those that are on the second card to be implemented for the several interfaces. In Fig. 1, Crystal Oscillator 1 clocks sixteen-bit Microprocessor Unit (MPU) 2, to which control and address lines are connected that also interface with the second card. Tri- state Task or printer interface Logic 3, that is bidirectional, isolates the MPU Bus 4 from the task interface .

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High Performance Printer Adapter

A versatile printer host system adapter is constructed by placing a microprocessor, memory and common logic on the same circuit card and using a second card for the specialized circuits to accommodate different physical links to various host processors.

(Image Omitted)

Fig. 1 illustrates the circuit components of the common card, while Fig. 2 shows those that are on the second card to be implemented for the several interfaces. In Fig. 1, Crystal Oscillator 1 clocks sixteen-bit Microprocessor Unit (MPU) 2, to which control and address lines are connected that also interface with the second card. Tri- state Task or printer interface Logic 3, that is bidirectional, isolates the MPU Bus 4 from the task interface . During Initial Microprogram Load (IML) the printer processor controls the interface and can access the Dynamic Random Access Memory (DRAM) 5, through DRAM Control 6 downloading microcode for execution by MPU 2. Addressing is through Latches 7. DRAM Controller 6 handles addressing, timing and refresh functions and runs in synchronous mode, permitting MPU 2 no-wait access except during refresh. Two eight-bit sets of Transceiver latches 8 allow data to either half of the data bus of MPU 2. Parity is either generated or checked at blocks 9, and contains necessary timing and controls at 10 for checking and forcing bad parity for diagnostics. Diagnostic register 11 is accessible by either MPU 2 or the printer microprocessor through tri-state Drivers 12 and...