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Method for Logging Error Status

IP.com Disclosure Number: IPCOM000034496D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Nakamura, T: AUTHOR [+2]

Abstract

Disclosed is a method for logging the error status in the diagnostic self-tests of a logic card. Referring to the figure, a logic card 1 to be tested includes a microprocessor unit (MPU) 2, a read-only memory (ROM) 3, a random- access memory (RAM) 4, and pads 5 and 6. A tester 7 includes an MPU 8, a register 9 and test probes 10 and 11. To test the logic card 1, the probes 10 and 11 are connected to the pads 5 and 6, respectively. During the test, the MPU 2 performs various diagnostic self-tests of the logic card 1, for example, MPU test, ROM test, and RAM test. The MPU 2 in the logic card 1 is so constructed as to perform a write operation to a particular address of the ROM 3 when the results of the diagnostic self-tests are in error.

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Method for Logging Error Status

Disclosed is a method for logging the error status in the diagnostic self-tests of a logic card. Referring to the figure, a logic card 1 to be tested includes a microprocessor unit (MPU) 2, a read-only memory (ROM) 3, a random- access memory (RAM) 4, and pads 5 and 6. A tester 7 includes an MPU 8, a register 9 and test probes 10 and 11. To test the logic card 1, the probes 10 and 11 are connected to the pads 5 and 6, respectively. During the test, the MPU 2 performs various diagnostic self-tests of the logic card 1, for example, MPU test, ROM test, and RAM test. The MPU 2 in the logic card 1 is so constructed as to perform a write operation to a particular address of the ROM 3 when the results of the diagnostic self-tests are in error. When the results of the MPU test are in error, the MPU 2 performs write operations to an address '80000' of the ROM 3. When the results of the ROS test are in error, the MPU 2 performs write operations to an address '80001' of the ROM 3. When the results of the RAM test are in error, the MPU 2 performs write operations to an address '80002' of the ROM 3. The write signal and the address in the write operations are supplied to the MPU 8 in the tester 7 through the pads 5 and 6 and the probes 10 and 11. The MPU 8 in the tester 7 recognizes the occurrence of the error in the diagnostic self-tests by monitoring the write signal and the address, and stores the address, such as '80000', '80001' and '80002'...