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Nonvolatile Ram Failure Rate Reduction Through the Use of Redundancy

IP.com Disclosure Number: IPCOM000034503D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 34K

Publishing Venue

IBM

Related People

Norgaard, SP: AUTHOR

Abstract

Often, computing systems have the need for nonvolatile storage that can be updated (both written and read) under microprocessor control. A nonvolatile random-access memory (NVRAM) device can be used to meet this need. An effective technique employing NVRAM uses redundancy to reduce the failure rate of the device. An NVRAM is made up of two devices. A static, random-access memory (SRAM) and an erasable, programmable, read only memory (EPROM). The failure rate of NVRAMs is relatively high compared to the rest of the large scale integration (LSI) logic on the card.

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Nonvolatile Ram Failure Rate Reduction Through the Use of Redundancy

Often, computing systems have the need for nonvolatile storage that can be updated (both written and read) under microprocessor control. A nonvolatile random-access memory (NVRAM) device can be used to meet this need. An effective technique employing NVRAM uses redundancy to reduce the failure rate of the device. An NVRAM is made up of two devices. A static, random-access memory (SRAM) and an erasable, programmable, read only memory (EPROM). The failure rate of NVRAMs is relatively high compared to the rest of the large scale integration (LSI) logic on the card. The failure modes of this device are: * cell/bit failure in either the SRAM or the EPROM * data line stuck at 0 or 1

* address line stuck at 0 or 1

* chip kill Redundancy techniques are used to recover from all of the failure modes except the last one. Additional failures, such as two of the device pins shorted together on the card, are also overcome. As an example, for nonvolatile storage requirements of 30 bytes plus 2 additional bytes of redundancy (a cyclic redundancy check (CRC) word) the total storage requirements would be 32 bytes (256 bits). Since the Xicor 2212 NVRAM is organized as 4x256 bits, four copies of the data can be stored in the device. This is done by storing the data vertically, as shown in Fig. 1. Note that the three columns on the right are identical (data written top to bottom) while the column on the left contains the same data but is written in reverse order (bottom to top). The technique used to recover the data from the NVRAM is done in two steps. The first pass assumes that there are cell and/or data line failures. If there are no errors or the assumption was correct, then the NVRAM data will be recovered, as described below. If that does not work, then address line failures are assumed. The recovery technique for this type of fault will be described later. To recover from cell and/or data line failures, the 4 data bits are read out from all 256 addresses. The left-most data bit at each address is not used at this time. The right-most three bits are used to d...