Browse Prior Art Database

Silicon, Elevated, Wireless Module Method for Making Engineering Changes

IP.com Disclosure Number: IPCOM000034507D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 4 page(s) / 100K

Publishing Venue

IBM

Related People

Kraus, CJ: AUTHOR [+3]

Abstract

A method has been developed for making high quality engineering changes (ECs) to multi-chip semiconductor modules without taking up excessive area. Silicon, Elevated, Wireless (SEW) technology is used in the proposal with buried EC lines connected to chip C4s. ECs are made by changing the appropriate chips, including wire direction, without using EC pads or jumper wires used. As the level of integration on chips increases, the opportunity to make an EC without changing at least one chip on the module is reduced. Previous technology required the use of top surface EC pads located around each chip on the multilayer ceramic (MLC) module. The pads were connected by discrete jumper wires to create the desired EC net. This technology will not be suitable for higher performance circuits of the future.

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Silicon, Elevated, Wireless Module Method for Making Engineering Changes

A method has been developed for making high quality engineering changes (ECs) to multi-chip semiconductor modules without taking up excessive area. Silicon, Elevated, Wireless (SEW) technology is used in the proposal with buried EC lines connected to chip C4s. ECs are made by changing the appropriate chips, including wire direction, without using EC pads or jumper wires used. As the level of integration on chips increases, the opportunity to make an EC without changing at least one chip on the module is reduced. Previous technology required the use of top surface EC pads located around each chip on the multilayer ceramic (MLC) module. The pads were connected by discrete jumper wires to create the desired EC net. This technology will not be suitable for higher performance circuits of the future.

(Image Omitted)

Buried EC technology uses lines buried in the MLC structure to provide long inter-chip wiring for the EC nets. While this results in improved performance, it still requires the use of top surface EC pads and 2-3 times the number of jumper wires as were previously needed. In the proposed SEW technology the silicon chips themselves are used to provide elevated bridges to interconnect buried EC lines without using dedicated EC C4s. This enables high performance EC nets to be created without changing the substrate, or requiring the use of EC pads, discrete jumper wires.

(Image Omitted)

In a cross-section of SEW technology, the buried line 1 (Fig. 1) in the MLC substrate 2 connects chip site 3 to other chip sites with a high quality impedance- controlled line. A group 4 of C4s are dedicated for EC use. These are preferably a pair of adjacent rows and columns down the center of the chip 5. Fig. 2, which is a top view through the chip, indicates the preferred configuration. Such an arrangement permit...