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Dynamic Random-Access Memory Refresh Using a Two-Cycle Direct Memory-Access Controller

IP.com Disclosure Number: IPCOM000034508D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Booth, JR: AUTHOR [+3]

Abstract

Both bus cycles of a two-cycle DMA controller are utilized to periodically refresh dynamic random-access memories (RAMs). This prevents performance degradation due to such refresh. It is necessary to periodically refresh a dynamic RAM through using only a row address strobe (RAS) signal and not allowing a column address strobe (CAS) signal to become active. This enables each row of the dynamic RAM to be refreshed periodically. An Intel 80188 microprocessor has a two-cycle, two-channel DMA controller. Since the first of the two bus cycles of the direct memory-access (DMA) controller is used only to read and the second bus cycle only to write, there would be a significant degradation performance if only the read bus cycle were utilized for refresh.

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Dynamic Random-Access Memory Refresh Using a Two-Cycle Direct Memory-Access Controller

Both bus cycles of a two-cycle DMA controller are utilized to periodically refresh dynamic random-access memories (RAMs). This prevents performance degradation due to such refresh. It is necessary to periodically refresh a dynamic RAM through using only a row address strobe (RAS) signal and not allowing a column address strobe (CAS) signal to become active. This enables each row of the dynamic RAM to be refreshed periodically. An Intel 80188 microprocessor has a two-cycle, two-channel DMA controller. Since the first of the two bus cycles of the direct memory-access (DMA) controller is used only to read and the second bus cycle only to write, there would be a significant degradation performance if only the read bus cycle were utilized for refresh. To avoid this, the write bus cycle of the DMA controller is also used to refresh. During the first bus cycle, which is a memory read, addresses A0-A8 on a line 1 are supplied to input pins D0 to D8 of a latch 2. These addresses are supplied from the DMA controller as part of the address of the dynamic RAM to be refreshed. The remaining addresses, A9-A19, are supplied over a line 3 to input pins D0 to D10 of a latch 4. When an address latch enable (ALE) signal goes negative, the addresses on the input pins D0-D8 of the latch 2 are transferred to output pins Q0-Q8 of the latch 2, and the addresses on the input pins D0-D10 of the latch 4 are transferred to output pins Q0-Q10 of the latch 4. Since the latch 4 has its ENABLE pin always grounded, addresses SA9-SA19 appear on a system bus line 5 as soon as they are received at the output pins Q0-Q10 of the latch 4. During the first bus cycle, the latch 2 has its ENABLE pin receive a low signal from an inverter 6 due to a high PCS6 signal; this is during the first bus cycle (the read portion) of the DMA controller. Thus, during the first bus cycle, addresses SA0-SA8 on the output pins Q0-Q8 of the latch 2 are transferred to a system bus line 7. The address on the bus line 7 is supplied to a dynamic RAM over a line 8 to cause one row in the dynamic RAM to be addressed. Thus, during the first bus cycle of the DMA controller, a first row is accessed in the dynamic RAM to refresh it. The address on the line 5 includes the CAS address but it is not...