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Emulation of IBM Pc Bus Operations by an 80188 Processor

IP.com Disclosure Number: IPCOM000034523D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 4 page(s) / 52K

Publishing Venue

IBM

Related People

Engelking, SR: AUTHOR [+3]

Abstract

This article describes a logic circuit that substitutes an Intel 80188 microprocessor for an Intel 8088 microprocessor -- with supporting components -- to create a standard IBM PC-1 bus interface compatible with existing IBM PC-1 adapters. The Intel 80188 is a lower cost and higher performance replacement for the original 8088-based component set, integrating on one chip the functions of the 8088 processor, the 8237 DMA controller, the 8254 timers, the 8259 interrupt controller, and various other support logic. The major obstacle to replacing the 8088 part set with the 80188 is differences in the DMA functions.

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Emulation of IBM Pc Bus Operations by an 80188 Processor

This article describes a logic circuit that substitutes an Intel 80188 microprocessor for an Intel 8088 microprocessor -- with supporting components - - to create a standard IBM PC-1 bus interface compatible with existing IBM PC-1 adapters. The Intel 80188 is a lower cost and higher performance replacement for the original 8088-based component set, integrating on one chip the functions of the 8088 processor, the 8237 DMA controller, the 8254 timers, the 8259 interrupt controller, and various other support logic. The major obstacle to replacing the 8088 part set with the 80188 is differences in the DMA functions. This circuit resolves the problem by using the 80188 programmable selects, protocol within the microprocessor, and a small amount of external logic to make the 80188 two- cycle DMA operations execute the same as the 8237 one-cycle DMA operations. The external logic is used with address assignments of the selects to generate the DMA control signals required by the 8237 DMA functions, but are not provided by the 80188 internal DMA logic. Specifically, the DMA acknowledge, terminal count, and several control signals are generated in a manner that emulates the corresponding IBM PC-1 bus signals. The 8237 DMA controller executes DMA transfers as one-cycle transfers between an I/O (input/output) adapter and a memory location. The 80188 DMA channels execute DMA transfers as two-cycle transfers from one memory location to another. Each DMA channel of the 8237 has an associated memory address register, DMA acknowledge signal, and transfer count register. The memory address register contains the address of the memory location of the data to be moved. The DMA acknowledge signal selects the I/O device handling the data to be moved. The 8237 also supplies a terminal count signal at the final transfer of a DMA operation. Each DMA channel of the 80188 has two associated memory address registers and a transfer count register. The memory address registers contain the addresses of the memory locations which are to be used as the source and destination of the data transfers. The 80188 DMA channels do not implement the DMA acknowledge or terminal count signals. An 8237 DMA operation is initiated when an I/O device requests a DMA service from the 8237 by activating its DMA request signal. The 8237 responds by taking control of the system bus for one cycle. During the one-cycle DMA transfer, the 8237 activates the I/O device's DMA acknowledge signal, places the appropriate memory location address on the bus address lines, and activates the necessary additional control signals. For a transfer from the I/O device to memory, this causes the I/O device to place the data to be moved on the bus data lines for subsequent capture by the memory. For a transfer from the memory to an I/O device, this causes the data to be read from the memory onto the bus data lines for subsequent capture by the I/O...