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Pipelined Processor Without Wait State

IP.com Disclosure Number: IPCOM000034526D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 68K

Publishing Venue

IBM

Related People

Buttimer, MD: AUTHOR

Abstract

In CPU design, considerable performance improvement may be obtained by employing a pipelined architecture in which the various activities carried out in the processing of an instruction are confined to their own particular cycle. This allows a full cycle time of the 'pipeline clock' for the activity to be completed before the result is passed on to the next stage of pipeline. In a pipelined CPU design, a series of stages are controlled by a pipleline clock. When two instructions are interdependent, timing problems occur which are normally solved by introducing a wait state. This disclosure adds logic which allows the results from one cycle to be used immediately in the next cycle. Comparators enable a result to be made available early during an operand prefetch of the following instruction.

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Pipelined Processor Without Wait State

In CPU design, considerable performance improvement may be obtained by employing a pipelined architecture in which the various activities carried out in the processing of an instruction are confined to their own particular cycle. This allows a full cycle time of the 'pipeline clock' for the activity to be completed before the result is passed on to the next stage of pipeline. In a pipelined CPU design, a series of stages are controlled by a pipleline clock. When two instructions are interdependent, timing problems occur which are normally solved by introducing a wait state. This disclosure adds logic which allows the results from one cycle to be used immediately in the next cycle. Comparators enable a result to be made available early during an operand prefetch of the following instruction. Consider a register-based CPU in which there are three separate pipelined phases: - operand fetch from the register array, Arithmetic Logic Unit (ALU) processing, and result storage back in the register array. The pipelined sequence of operations is shown in Fig. 1 below.

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Fig. 1 A problem occurs where the computed result of instruction 'n' is required as an operand to the following instructon 'n+1'. As the storage of the result of instruction 'n' in general register Rx occurs in time-slot T3, and the fetch of the operands (assumed to include the contents of the same general register Rx) occurs in time-slot T2, the 'old' contents of Rx will be erroneously used in the execution of instruction 'n+1'. Thus a timing incompatibility occurs in the pipeline when two instructions are interdependent. Fig. 2 illustrates the principle components of a register-based CPU design. Registers A, B, C, D, E and F are the pipeline storage registers which are clocked by the pipeline clock Cp1. Registers A, B and C store the instructions for the pipeline stages; A supplies the read addresses (...