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Memory Controller Having Self-Initialize Function

IP.com Disclosure Number: IPCOM000034531D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Hatori, M: AUTHOR [+2]

Abstract

This article describes a concept of providing a self-initialize function in a memory controller. This controller is set up with memory information, such as memory access speed, memory address, controller I/O address, using CPU start-up time. The memory system with this controller needs no CPU initialization. Three major components are provided in the controller, which are four programmable register units, a set-up sequencer and a memory. A part of the memory contains information about this memory system. The information is on memory size (range in address space), memory base address, I/O address for memory bank switch and memory wait. After a power-on reset, the set-up sequencer reads this memory information from the memory and sets the values to the corresponding registers.

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Memory Controller Having Self-Initialize Function

This article describes a concept of providing a self-initialize function in a memory controller. This controller is set up with memory information, such as memory access speed, memory address, controller I/O address, using CPU start-up time. The memory system with this controller needs no CPU initialization. Three major components are provided in the controller, which are four programmable register units, a set-up sequencer and a memory. A part of the memory contains information about this memory system. The information is on memory size (range in address space), memory base address, I/O address for memory bank switch and memory wait. After a power-on reset, the set-up sequencer reads this memory information from the memory and sets the values to the corresponding registers. This operation is done in parallel with CPU initialization time. Each register is checked by a comparator on the bus condition, such as memory read/write and I/O read/write. When the expected condition comes to the pre-settled register, the comparator outputs a signal for controlling the address and control lines to the memory. The CPU can access the memory.

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