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Random-Access Memory Output Latch Reset Circuit

IP.com Disclosure Number: IPCOM000034551D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Wissel, L: AUTHOR

Abstract

Detection of a word line failure in a random-access memory (RAM) is facilitated through the introduction of a new reset circuit for the output latches. By introducing a new reset device to the output latch of a RAM, a positive reset is made early in each access cycle so that old data with parity is not retained. The resulting latch is better suited for error detection in the event of a reliability failure of a word line. Also, the new reset device allows a reduced access time and is self-timed to adjust for the size of memory. During RAM restore time both of the differential inputs to the output latch are low. During a RAM cell access, one of the differential inputs (bit lines) falls and one of the differential outputs rises.

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Random-Access Memory Output Latch Reset Circuit

Detection of a word line failure in a random-access memory (RAM) is facilitated through the introduction of a new reset circuit for the output latches. By introducing a new reset device to the output latch of a RAM, a positive reset is made early in each access cycle so that old data with parity is not retained. The resulting latch is better suited for error detection in the event of a reliability failure of a word line. Also, the new reset device allows a reduced access time and is self-timed to adjust for the size of memory. During RAM restore time both of the differential inputs to the output latch are low. During a RAM cell access, one of the differential inputs (bit lines) falls and one of the differential outputs rises. When there is no differential input signal to the sense amplifiers during access, both bit lines stay at the low voltage level set during restore. Therefore, if there is a word line open (a common reliability fail mode at the second level metal), neither of the bit lines discharge, and thus the output latch retains the old data. Because the old data satisfies parity, error detection circuits do not indicate that a failure has occurred. Referring to Fig. 1, the RAM output latch is enabled by the READ signal generated by NAND gate 10. When the output latch is enabled, it sets according to which bit line is high. If neither bit line rises, the output latch will retain old data. By adding a reset d...