Browse Prior Art Database

Flip-Chip Wire Bond First Level Package

IP.com Disclosure Number: IPCOM000034558D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Gruber, H: AUTHOR [+4]

Abstract

A package concept is proposed by which large numbers of external connections to a chip are obtained in conjunction with MLC (multilayer ceramic) packages, without exceeding the reliability requirements for a C4 footprint. The external chip connections are divided into two groups. One group forms the C4 footprint with a distance-to-neutral point that ensures the required reliability, and the other group is wire bonded from the chip periphery to the MLC pads next to the chip. The wire-bond connections are not affected by a thermal mismatch of the MLC substrate and the chip. The wire-bond connections include all simultaneously switching drivers along with the power lines to reduce delta I and coupled noise. Separate power feeding of drivers and internal logic is accomplished by the C4 power input and by wire bonding.

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Flip-Chip Wire Bond First Level Package

A package concept is proposed by which large numbers of external connections to a chip are obtained in conjunction with MLC (multilayer ceramic) packages, without exceeding the reliability requirements for a C4 footprint. The external chip connections are divided into two groups. One group forms the C4 footprint with a distance-to-neutral point that ensures the required reliability, and the other group is wire bonded from the chip periphery to the MLC pads next to the chip. The wire-bond connections are not affected by a thermal mismatch of the MLC substrate and the chip. The wire-bond connections include all simultaneously switching drivers along with the power lines to reduce delta I and coupled noise. Separate power feeding of drivers and internal logic is accomplished by the C4 power input and by wire bonding. The figure shows that chip 1 comprises C4 metallurgy 2 for center footprint 3 and wire bond pads 4 for peripheral footprint 5. The center footprint supplies power to the internal logic circuits and provides all receiver connections to the chip. The peripheral footprint supplies power to the external drivers, in addition to providing all driver output connections from the chip. The chip is placed in an aluminum frame 6 on the wire bonder. All peripheral pads (power connections and driver outputs) are connected to aluminum frame 6 by wire bonding. The frame/chip assembly is placed on the C4 footprint of the substrate and joined by soldering. The subst...