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Method of Improving the Yield of VLSI Logic Chips by Using a Variable Wiring Channel Pitch

IP.com Disclosure Number: IPCOM000034562D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 4 page(s) / 95K

Publishing Venue

IBM

Related People

Klein, K: AUTHOR [+4]

Abstract

The wiring of VLSI logic chips is limited. For maximum gate density, such chips use the minimum wiring channel pitch that is technically feasible. A line width and spacing of, say, 1.2 and 1.3 mm, respectively, yield a wiring channel pitch of 2.5 mm. Automatic wiring programs permit using 60 to 70% of the wiring channels available. The distance between wires is constant, in the above example, amounting to 1.3 mm for neighboring wires and to 3.8 mm for wires between which there is an empty channel. This does not lead to optimum chip yield. Therefore, it is proposed that the space of an unused channel be allocated to the neighboring wires. The respective immediate neighbor is displaced 2 steps towards the unused channel, allowing the next wire to follow by 1 step. The proposed method is shown in Figs. 1A to 1C.

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Page 1 of 4

Method of Improving the Yield of VLSI Logic Chips by Using a Variable Wiring Channel Pitch

The wiring of VLSI logic chips is limited. For maximum gate density, such chips use the minimum wiring channel pitch that is technically feasible. A line width and spacing of, say, 1.2 and 1.3 mm, respectively, yield a wiring channel pitch of 2.5 mm. Automatic wiring programs permit using 60 to 70% of the wiring channels available. The distance between wires is constant, in the above example, amounting to 1.3 mm for neighboring wires and to 3.8 mm for wires between which there is an empty channel. This does not lead to optimum chip yield. Therefore, it is proposed that the space of an unused channel be allocated to the neighboring wires. The respective immediate neighbor is displaced 2 steps towards the unused channel, allowing the next wire to follow by 1 step. The proposed method is shown in Figs. 1A to 1C.

(Image Omitted)

The physical design sequence is as follows:

1. Generate channelized wiring data as usual.

2. Attach different wire codes (Table 1) to each line

part with

different neighborhood relations. Code Neighborhood Relations Preferred Possible

Used

Steps Steps

Steps

A no neighbors 0 -2 +2

-

B lower (right) neighbor

only +2 0 +2 -

C upper (left) neighbor

only -2 -2 0 -

D between neighbors 0 -1 +1

- +1 lower line has code B - -

+1 +2 lower line has code +1 - -

+2 Code

Neighborhood Relations Preferred Possible

Used

Steps Steps

Steps -1 upper line has code C - -

-1 -2 upper line has code -1 - -

-2 0 neighbors +1, 0, -1 - -

0

1

Page 2 of 4

Table 1 3. Lines of code A-0 are selected such that there are no un necessary steps. A code +2 line part is followed,

for example, by a code A part. Then, the A part

goes to +2, yielding a common straight line of

code +2.

Finally, only codes +2, +1, 0, -1, -2 are

permissible. 4. The step size in mm is made a physical rule. The line parts

and the associated vias are displaced by this

amount from the center of the wiring channel

during the generation of different wiring

structures. For the described - 2 step, the step size is 1/5 of the channel pitch (say, 0.5 mm). As shown in the figures, the wire width of the displaced lines is also increased. The method has the fo...