Browse Prior Art Database

High-Performance Processor

IP.com Disclosure Number: IPCOM000034566D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 65K

Publishing Venue

IBM

Related People

Klink, E: AUTHOR [+2]

Abstract

For obtaining short electrical signal transmission lines between the individual semiconductor chips of a processor, a logic or memory chip is used to connect the chip and the wiring carrier. Fig. 1 shows that the wiring technology employed comprises only solder ball connections 7. The critical paths of the processor are considerably reduced. Through an opening of chip carrier 3 and by paste 4, the rear side of chip 1 is thermally connected to cooling plate 5. Thus, chips 1 and 2 can be ideally cooled from their rear side.

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High-Performance Processor

For obtaining short electrical signal transmission lines between the individual semiconductor chips of a processor, a logic or memory chip is used to connect the chip and the wiring carrier. Fig. 1 shows that the wiring technology employed comprises only solder ball connections 7. The critical paths of the processor are considerably reduced. Through an opening of chip carrier 3 and by paste 4, the rear side of chip 1 is thermally connected to cooling plate 5. Thus, chips 1 and 2 can be ideally cooled from their rear side. The connected chips 1 and 2 may be o a cache chip and a PU chip

o a PU/cache chip and a coprocessor

o a floating-point processor and a vector processor

o a cache and another cache

o a PC bus adapter and a PC bus driver chip

o an optical GaAs diode chip and a bus adapter Fig. 2 shows another application for the proposed technology. Chip 1 is arranged in a recess of the multilayer multichip carrier 3. The typical advantages of this arrangement are generally the same as those shown in Fig. 3. Simple chip carriers with soldered contact pins 6 may be used. The depth of the recess in chip carrier 3 roughly matches the size of chip 1, paste 4 being used as a filler, so that the upper edges of the carrier and chip are flush. Smaller height variations are compensated for by solder balls 7. The chips may be wired in the form of networks both on the carrier surface, using a surface thin- film process, and in the multilayer multichip carrier, partly below the recesses.

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A suitable process technology consists in the use of solder balls 7 with different melting points. First, the low-melting point solder balls of chips 1 and 2 and immediate...