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High Performance Totem-Pole Drive

IP.com Disclosure Number: IPCOM000034598D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Lundberg, MB: AUTHOR [+2]

Abstract

Two MOSFET devices, which are arranged in a totem-pole configuration, have their gates capacitively coupled to a drive signal to minimize DC losses. Switching losses are minimized by using a parallel diode/ inductance in the gate drive circuit. The lower voltage level of the gate drive signal is translated to the high voltage level at the source of the MOSFET. (Image Omitted) A high current, high speed driver 1 (Fig. 1) inverts a logic signal having an amplitude of 5 volts and increases its amplitude to 15 volts. When the output of the driver 1 goes low upon receiving a positive input, it causes a MOSFET 2 to be turned on and a MOSFET 3 to be turned off. The MOSFET 2 has its source connected to +V, which is 45 volts, for example, and the MOSFET 3 has its drain connected to -V, which is -45 volts, for example.

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High Performance Totem-Pole Drive

Two MOSFET devices, which are arranged in a totem-pole configuration, have their gates capacitively coupled to a drive signal to minimize DC losses. Switching losses are minimized by using a parallel diode/ inductance in the gate drive circuit. The lower voltage level of the gate drive signal is translated to the high voltage level at the source of the MOSFET.

(Image Omitted)

A high current, high speed driver 1 (Fig. 1) inverts a logic signal having an amplitude of 5 volts and increases its amplitude to 15 volts. When the output of the driver 1 goes low upon receiving a positive input, it causes a MOSFET 2 to be turned on and a MOSFET 3 to be turned off. The MOSFET 2 has its source connected to +V, which is 45 volts, for example, and the MOSFET 3 has its drain connected to -V, which is -45 volts, for example. The drive signal for turning on the MOSFET 2 is supplied through a capacitor 4 and an inductance 5 to a gate 6 of the MOSFET 2. Resistors 7 and 8 and an NPN transistor 9, which has its base supplied with +15 volts, provide a bias circuit to the gate 6 of the MOSFET
2. The current level in the bias circuit is very small since it has only to maintain a voltage on the gate 6, which has a very high impedance, of the MOSFET 2. When the input signal to the driver 1 goes to zero, the high output of the driver 1 turns on the MOSFET 3 by being supplied through a capacitor 12 and an inductance 13 to a gate 14 of the MOSFET 3. The curr...