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Processor Verification Test Process

IP.com Disclosure Number: IPCOM000034606D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Breyfogle, FW: AUTHOR [+3]

Abstract

Processor or logic devices often have so many input combination possibilities that it is impossible to verify that all possible input and state conditions yield the desired response outputs. A process is described in which a "reasonable" number of rigorously selected input and state condition combinations are tested for correct output responses. This process is intended for processor simulation test; however, the concept can be applied to other areas of software and engineering verification tests. Assume that a device to be certified has 100 input level and state condition possibilities. In this example, there are 2100 possible combinations (1.26 x 1030). The testing of all possible combinations is not practical. Assume further that failures are caused by several things "working together", e.g.

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Processor Verification Test Process

Processor or logic devices often have so many input combination possibilities that it is impossible to verify that all possible input and state conditions yield the desired response outputs. A process is described in which a "reasonable" number of rigorously selected input and state condition combinations are tested for correct output responses. This process is intended for processor simulation test; however, the concept can be applied to other areas of software and engineering verification tests. Assume that a device to be certified has 100 input level and state condition possibilities. In this example, there are 2100 possible combinations (1.26 x 1030). The testing of all possible combinations is not practical. Assume further that failures are caused by several things "working together", e.g., several variables at a certain level. If all possibilities in the above example are tested, all 100 variables are each set to a certain level to cause a problem. This is referred to as 100th level "interaction" coverage. It is reasonable to assume that "all" variables don't have to be set to a certain level for a problem to occur. A significant number of test trials can therefore be "saved" by designing a test which "certifies" a lower level of "interaction."

For example, a tester may wish to "certify" up to the 8th level "interaction." In this case, a satisfactory response on the complete test would yield the statement: "the tester is 100% confident that up to 8 variables/states cannot be put in any combination to yield unsatisfactory performance." Note, the level of "interaction" which is to be "certified" should be dependent upon economics with consideration to the number of input variables. The following steps describe a process to develop a simulation test case to "certify" a processor. 1. Subdivide the processor into "functional" areas to perform the

following test. Note, after these "functional"

area tests are

complete, this test process is repeated on the

complete

processor package.

2. Design a test to certify that there are no two factors that

"work together" to yield an incorrect response.

Two-factor "interaction" confou...